Lines Matching +full:x +full:- +full:rc
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2012-2019 ARM Limited or its affiliates. */
94 { .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw },
95 { .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw },
96 { .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw },
97 { .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw },
98 { .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw },
111 dev_dbg(dev, "Cache params previous: 0x%08X\n", cache_params); in init_cc_cache_params()
113 /* non cached or write-back, write allocate */ in init_cc_cache_params()
114 val = drvdata->coherent ? 0xb : 0x2; in init_cc_cache_params()
128 drvdata->cache_params = cache_params; in init_cc_cache_params()
130 dev_dbg(dev, "Cache params current: 0x%08X\n", cache_params); in init_cc_cache_params()
132 if (drvdata->hw_rev <= CC_HW_REV_710) in init_cc_cache_params()
137 dev_dbg(dev, "ACE-const previous: 0x%08X\n", ace_const); in init_cc_cache_params()
139 /* system or outer-sharable */ in init_cc_cache_params()
140 val = drvdata->coherent ? 0x2 : 0x3; in init_cc_cache_params()
150 dev_dbg(dev, "ACE-const current: 0x%08X\n", ace_const); in init_cc_cache_params()
152 drvdata->ace_const = ace_const; in init_cc_cache_params()
196 dev_dbg(dev, "Got IRR=0x%08X\n", irr); in cc_isr()
203 /* clear interrupt - must be before processing events */ in cc_isr()
206 drvdata->irq = irr; in cc_isr()
207 /* Completion interrupt - most probable */ in cc_isr()
208 if (irr & drvdata->comp_mask) { in cc_isr()
209 /* Mask all completion interrupts - will be unmasked in in cc_isr()
212 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask); in cc_isr()
213 irr &= ~drvdata->comp_mask; in cc_isr()
219 /* Mask interrupt - will be unmasked in Deferred service in cc_isr()
233 dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n", in cc_isr()
240 dev_dbg_ratelimited(dev, "IRR includes unknown cause bits (0x%08X)\n", in cc_isr()
254 if (drvdata->hw_rev <= CC_HW_REV_712) in cc_wait_for_reset_completion()
280 if (drvdata->hw_rev <= CC_HW_REV_712) { in init_cc_regs()
283 dev_dbg(dev, "AXIM_CFG=0x%08X\n", in init_cc_regs()
289 dev_dbg(dev, "IRR=0x%08X\n", val); in init_cc_regs()
293 val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK; in init_cc_regs()
295 if (drvdata->hw_rev >= CC_HW_REV_712) in init_cc_regs()
300 cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), drvdata->cache_params); in init_cc_regs()
301 if (drvdata->hw_rev >= CC_HW_REV_712) in init_cc_regs()
302 cc_iowrite(drvdata, CC_REG(AXIM_ACE_CONST), drvdata->ace_const); in init_cc_regs()
311 struct device *dev = &plat_dev->dev; in init_cc_resources()
312 struct device_node *np = dev->of_node; in init_cc_resources()
318 int rc = 0; in init_cc_resources() local
322 return -ENOMEM; in init_cc_resources()
325 new_drvdata->hw_rev_name = hw_rev->name; in init_cc_resources()
326 new_drvdata->hw_rev = hw_rev->rev; in init_cc_resources()
327 new_drvdata->std_bodies = hw_rev->std_bodies; in init_cc_resources()
329 if (hw_rev->rev >= CC_HW_REV_712) { in init_cc_resources()
330 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP); in init_cc_resources()
331 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712); in init_cc_resources()
332 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712); in init_cc_resources()
334 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8); in init_cc_resources()
335 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630); in init_cc_resources()
336 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630); in init_cc_resources()
339 new_drvdata->comp_mask = CC_COMP_IRQ_MASK; in init_cc_resources()
342 new_drvdata->plat_dev = plat_dev; in init_cc_resources()
347 new_drvdata->clk = clk; in init_cc_resources()
349 new_drvdata->coherent = of_dma_is_coherent(np); in init_cc_resources()
355 new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs); in init_cc_resources()
356 if (IS_ERR(new_drvdata->cc_base)) in init_cc_resources()
357 return PTR_ERR(new_drvdata->cc_base); in init_cc_resources()
359 dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name, in init_cc_resources()
361 dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n", in init_cc_resources()
362 &req_mem_cc_regs->start, new_drvdata->cc_base); in init_cc_resources()
369 init_completion(&new_drvdata->hw_queue_avail); in init_cc_resources()
371 if (!dev->dma_mask) in init_cc_resources()
372 dev->dma_mask = &dev->coherent_dma_mask; in init_cc_resources()
375 rc = dma_set_coherent_mask(dev, dma_mask); in init_cc_resources()
376 if (rc) { in init_cc_resources()
379 return rc; in init_cc_resources()
382 rc = clk_prepare_enable(new_drvdata->clk); in init_cc_resources()
383 if (rc) { in init_cc_resources()
385 return rc; in init_cc_resources()
388 new_drvdata->sec_disabled = cc_sec_disable; in init_cc_resources()
394 rc = pm_runtime_get_sync(dev); in init_cc_resources()
395 if (rc < 0) { in init_cc_resources()
396 dev_err(dev, "pm_runtime_get_sync() failed: %d\n", rc); in init_cc_resources()
405 if (hw_rev->rev <= CC_HW_REV_712) { in init_cc_resources()
407 val = cc_ioread(new_drvdata, new_drvdata->sig_offset); in init_cc_resources()
408 if (val != hw_rev->sig) { in init_cc_resources()
409 dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", in init_cc_resources()
410 val, hw_rev->sig); in init_cc_resources()
411 rc = -EINVAL; in init_cc_resources()
415 hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset); in init_cc_resources()
419 if (val != hw_rev->pidr_0124) { in init_cc_resources()
420 dev_err(dev, "Invalid CC PIDR: PIDR0124=0x%08X != expected=0x%08X\n", in init_cc_resources()
421 val, hw_rev->pidr_0124); in init_cc_resources()
422 rc = -EINVAL; in init_cc_resources()
428 if (val != hw_rev->cidr_0123) { in init_cc_resources()
429 dev_err(dev, "Invalid CC CIDR: CIDR0123=0x%08X != expected=0x%08X\n", in init_cc_resources()
430 val, hw_rev->cidr_0123); in init_cc_resources()
431 rc = -EINVAL; in init_cc_resources()
443 if (new_drvdata->std_bodies & CC_STD_NIST) { in init_cc_resources()
445 new_drvdata->std_bodies = CC_STD_OSCCA; in init_cc_resources()
450 rc = -EINVAL; in init_cc_resources()
457 new_drvdata->sec_disabled |= !!val; in init_cc_resources()
459 if (!new_drvdata->sec_disabled) { in init_cc_resources()
460 new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK; in init_cc_resources()
461 if (new_drvdata->std_bodies & CC_STD_NIST) in init_cc_resources()
462 new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK; in init_cc_resources()
466 if (new_drvdata->sec_disabled) in init_cc_resources()
470 dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X/0x%8X, Driver version %s\n", in init_cc_resources()
471 hw_rev->name, hw_rev_pidr, sig_cidr, DRV_MODULE_VERSION); in init_cc_resources()
473 rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "ccree", in init_cc_resources()
475 if (rc) { in init_cc_resources()
483 rc = init_cc_regs(new_drvdata); in init_cc_resources()
484 if (rc) { in init_cc_resources()
489 rc = cc_debugfs_init(new_drvdata); in init_cc_resources()
490 if (rc) { in init_cc_resources()
495 rc = cc_fips_init(new_drvdata); in init_cc_resources()
496 if (rc) { in init_cc_resources()
497 dev_err(dev, "cc_fips_init failed 0x%x\n", rc); in init_cc_resources()
500 rc = cc_sram_mgr_init(new_drvdata); in init_cc_resources()
501 if (rc) { in init_cc_resources()
506 new_drvdata->mlli_sram_addr = in init_cc_resources()
508 if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) { in init_cc_resources()
509 rc = -ENOMEM; in init_cc_resources()
513 rc = cc_req_mgr_init(new_drvdata); in init_cc_resources()
514 if (rc) { in init_cc_resources()
519 rc = cc_buffer_mgr_init(new_drvdata); in init_cc_resources()
520 if (rc) { in init_cc_resources()
528 rc = cc_hash_alloc(new_drvdata); in init_cc_resources()
529 if (rc) { in init_cc_resources()
535 rc = cc_cipher_alloc(new_drvdata); in init_cc_resources()
536 if (rc) { in init_cc_resources()
541 rc = cc_aead_alloc(new_drvdata); in init_cc_resources()
542 if (rc) { in init_cc_resources()
574 clk_disable_unprepare(new_drvdata->clk); in init_cc_resources()
575 return rc; in init_cc_resources()
586 struct device *dev = &plat_dev->dev; in cleanup_cc_resources()
601 clk_disable_unprepare(drvdata->clk); in cleanup_cc_resources()
606 if (drvdata->hw_rev >= CC_HW_REV_712) in cc_get_default_hash_len()
614 int rc; in ccree_probe() local
615 struct device *dev = &plat_dev->dev; in ccree_probe()
618 rc = init_cc_resources(plat_dev); in ccree_probe()
619 if (rc) in ccree_probe()
620 return rc; in ccree_probe()
629 struct device *dev = &plat_dev->dev; in ccree_remove()