Lines Matching +full:0 +full:x4800

20 #define REVISION_MASK				0xF
23 #define AM33XX_800M_ARM_MPU_MAX_FREQ		0x1E2F
24 #define AM43XX_600M_ARM_MPU_MAX_FREQ		0xFFA
32 #define DRA7_EFUSE_NOM_MPU_OPP			BIT(0)
37 #define OMAP3_CONTROL_DEVICE_STATUS		0x4800244C
38 #define OMAP3_CONTROL_IDCODE			0x4830A204
39 #define OMAP34xx_ProdID_SKUID			0x4830A20C
40 #define OMAP3_SYSCON_BASE	(0x48000000 + 0x2000 + 0x270)
110 	.efuse_offset = 0x07fc,
111 	.efuse_mask = 0x1fff,
112 	.rev_offset = 0x600,
119 	.efuse_offset = 0x0610,
120 	.efuse_mask = 0x3f,
121 	.rev_offset = 0x600,
127 	.efuse_offset = 0x020c,
128 	.efuse_mask = 0xf80000,
130 	.rev_offset = 0x204,
136  *  CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
137  *  Control OMAP Status Register 15:0 (Address 0x4800 244C)
145  *  Register 0x4830A20C [ProdID.SKUID] [0:3]
146  *    0x0 for normal 600/430MHz device.
147  *    0x8 for 720/520MHz device.
162  *  CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
163  *  Control Device Status Register 15:0 (Address 0x4800 244C)
167  *     0 800/600 MHz
171  *  There is no 0x4830A20C [ProdID.SKUID] register (exists but
172  *    seems to always read as 0).
195 	.efuse_shift = 0,
196 	.efuse_mask = 0,
240 	return 0;  in ti_cpufreq_get_efuse()
278 	return 0;  in ti_cpufreq_get_rev()
294 	return 0;  in ti_cpufreq_setup_syscon_register()
344 	opp_data->cpu_dev = get_cpu_device(0);  in ti_cpufreq_probe()
364 	 *	0 - SoC Revision  in ti_cpufreq_probe()
367 	ret = ti_cpufreq_get_rev(opp_data, &version[0]);  in ti_cpufreq_probe()
383 	if (ret < 0) {  in ti_cpufreq_probe()
391 	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);  in ti_cpufreq_probe()
393 	return 0;  in ti_cpufreq_probe()
411 	return 0;  in ti_cpufreq_init()