1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/nvmem-consumer.h>
29 	STEP,  enumerator
43 	{ .id = "step" },
81 	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",  in imx6q_set_target()
114 	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it  in imx6q_set_target()
115 	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it  in imx6q_set_target()
116 	 *  - Disable pll2_pfd2_396m_clk  in imx6q_set_target()
135 		clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);  in imx6q_set_target()
136 		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);  in imx6q_set_target()
142 		clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);  in imx6q_set_target()
143 		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);  in imx6q_set_target()
167 	/* PLL1 is only needed until after ARM-PODF is set. */  in imx6q_set_target()
171 	/* scaling down?  scale voltage after frequency */  in imx6q_set_target()
176 				 "failed to scale vddarm down: %d\n", ret);  in imx6q_set_target()
179 			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);  in imx6q_set_target()
183 				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);  in imx6q_set_target()
192 	policy->clk = clks[ARM].clk;  in imx6q_cpufreq_init()
194 	policy->suspend_freq = max_freq;  in imx6q_cpufreq_init()
207 	.name = "imx6q-cpufreq",
225 	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {  in imx6q_opp_check_speed_grading()
230 		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");  in imx6q_opp_check_speed_grading()
232 			return -ENOENT;  in imx6q_opp_check_speed_grading()
238 			return -EFAULT;  in imx6q_opp_check_speed_grading()
245 		 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.  in imx6q_opp_check_speed_grading()
282 	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {  in imx6ul_opp_check_speed_grading()
290 		np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");  in imx6ul_opp_check_speed_grading()
293 						     "fsl,imx6ull-ocotp");  in imx6ul_opp_check_speed_grading()
295 			return -ENOENT;  in imx6ul_opp_check_speed_grading()
301 			return -EFAULT;  in imx6ul_opp_check_speed_grading()
351 		return -ENODEV;  in imx6q_cpufreq_probe()
354 	np = of_node_get(cpu_dev->of_node);  in imx6q_cpufreq_probe()
357 		return -ENOENT;  in imx6q_cpufreq_probe()
373 	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||  in imx6q_cpufreq_probe()
374 			PTR_ERR(soc_reg) == -EPROBE_DEFER ||  in imx6q_cpufreq_probe()
375 			PTR_ERR(pu_reg) == -EPROBE_DEFER) {  in imx6q_cpufreq_probe()
376 		ret = -EPROBE_DEFER;  in imx6q_cpufreq_probe()
382 		ret = -ENOENT;  in imx6q_cpufreq_probe()
420 		ret = -ENOMEM;  in imx6q_cpufreq_probe()
424 	prop = of_find_property(np, "fsl,soc-operating-points", NULL);  in imx6q_cpufreq_probe()
425 	if (!prop || !prop->value)  in imx6q_cpufreq_probe()
430 	 * voltage like <freq-kHz vol-uV>.  in imx6q_cpufreq_probe()
432 	nr = prop->length / sizeof(u32);  in imx6q_cpufreq_probe()
437 		val = prop->value;  in imx6q_cpufreq_probe()
451 …dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!…  in imx6q_cpufreq_probe()
454 		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)  in imx6q_cpufreq_probe()
455 			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;  in imx6q_cpufreq_probe()
458 	if (of_property_read_u32(np, "clock-latency", &transition_latency))  in imx6q_cpufreq_probe()
465 	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);  in imx6q_cpufreq_probe()
469 		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);  in imx6q_cpufreq_probe()
479 	max_freq = freq_table[--num].frequency;  in imx6q_cpufreq_probe()
537 		.name	= "imx6q-cpufreq",
544 MODULE_ALIAS("platform:imx6q-cpufreq");