1 // SPDX-License-Identifier: GPL-2.0+
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
26 #include "cpufreq-dt.h"
49 #define  ARMADA_37XX_NB_VDD_EN		BIT(30)
60 #define	 ARMADA_37XX_AVS_ENABLE		BIT(30)
79 /*  AVS value for the corresponding voltage (in mV) */
168 		 * Set cpu divider based on the pre-computed array in  in armada37xx_cpufreq_dvfs_setup()
189  * the round-up closest to the target voltage value.
195 	/* Find out the round-up closest supported voltage value */  in armada_37xx_avs_val_match()
205 		avs = ARRAY_SIZE(avs_map) - 1;  in armada_37xx_avs_val_match()
213  * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
215  * - L1 voltage should be about 100mv smaller than L0 voltage
216  * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
240 	dvfs->avs[0] = l0_vdd_min;  in armada37xx_cpufreq_avs_configure()
244 		 * If L0 voltage is smaller than 1000mv, then all VDD sets  in armada37xx_cpufreq_avs_configure()
250 			dvfs->avs[load_level] = avs_min;  in armada37xx_cpufreq_avs_configure()
257 		if (dvfs->cpu_freq_max >= 1000*1000*1000) {  in armada37xx_cpufreq_avs_configure()
258 			if (dvfs->cpu_freq_max >= 1200*1000*1000)  in armada37xx_cpufreq_avs_configure()
262 			dvfs->avs[0] = dvfs->avs[1] = avs_min;  in armada37xx_cpufreq_avs_configure()
269 	 * L1 voltage is equal to L0 voltage - 100mv and it must be  in armada37xx_cpufreq_avs_configure()
270 	 * larger than 1000mv  in armada37xx_cpufreq_avs_configure()
273 	target_vm = avs_map[l0_vdd_min] - 100;  in armada37xx_cpufreq_avs_configure()
275 	dvfs->avs[1] = armada_37xx_avs_val_match(target_vm);  in armada37xx_cpufreq_avs_configure()
278 	 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must  in armada37xx_cpufreq_avs_configure()
279 	 * be larger than 1000mv  in armada37xx_cpufreq_avs_configure()
281 	target_vm = avs_map[l0_vdd_min] - 150;  in armada37xx_cpufreq_avs_configure()
283 	dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);  in armada37xx_cpufreq_avs_configure()
290 	if (dvfs->cpu_freq_max >= 1000*1000*1000) {  in armada37xx_cpufreq_avs_configure()
293 		if (dvfs->cpu_freq_max >= 1200*1000*1000)  in armada37xx_cpufreq_avs_configure()
298 		if (avs_min_l1 > dvfs->avs[0])  in armada37xx_cpufreq_avs_configure()
299 			avs_min_l1 = dvfs->avs[0];  in armada37xx_cpufreq_avs_configure()
301 		if (dvfs->avs[1] < avs_min_l1)  in armada37xx_cpufreq_avs_configure()
302 			dvfs->avs[1] = avs_min_l1;  in armada37xx_cpufreq_avs_configure()
327 		avs_val = dvfs->avs[load_level];  in armada37xx_cpufreq_avs_setup()
328 		regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),  in armada37xx_cpufreq_avs_setup()
372 	regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1);  in armada37xx_cpufreq_suspend()
373 	regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3);  in armada37xx_cpufreq_suspend()
374 	regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD,  in armada37xx_cpufreq_suspend()
375 		    &state->nb_cpu_load);  in armada37xx_cpufreq_suspend()
376 	regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod);  in armada37xx_cpufreq_suspend()
386 	armada37xx_cpufreq_disable_dvfs(state->regmap);  in armada37xx_cpufreq_resume()
388 	regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1);  in armada37xx_cpufreq_resume()
389 	regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3);  in armada37xx_cpufreq_resume()
390 	regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD,  in armada37xx_cpufreq_resume()
391 		     state->nb_cpu_load);  in armada37xx_cpufreq_resume()
398 	regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod);  in armada37xx_cpufreq_resume()
416 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");  in armada37xx_cpufreq_driver_init()
418 		return -ENODEV;  in armada37xx_cpufreq_driver_init()
421 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");  in armada37xx_cpufreq_driver_init()
424 		return -ENODEV;  in armada37xx_cpufreq_driver_init()
427 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs");  in armada37xx_cpufreq_driver_init()
445 		return -ENODEV;  in armada37xx_cpufreq_driver_init()
467 		return -EINVAL;  in armada37xx_cpufreq_driver_init()
473 		return -EINVAL;  in armada37xx_cpufreq_driver_init()
480 		return -ENOMEM;  in armada37xx_cpufreq_driver_init()
483 	armada37xx_cpufreq_state->regmap = nb_pm_base;  in armada37xx_cpufreq_driver_init()
488 	armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);  in armada37xx_cpufreq_driver_init()
493 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;  in armada37xx_cpufreq_driver_init()
494 		freq = base_frequency / dvfs->divider[load_lvl];  in armada37xx_cpufreq_driver_init()
509 	pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,  in armada37xx_cpufreq_driver_init()
515 	armada37xx_cpufreq_state->cpu_dev = cpu_dev;  in armada37xx_cpufreq_driver_init()
516 	armada37xx_cpufreq_state->pdev = pdev;  in armada37xx_cpufreq_driver_init()
523 	/* clean-up the already added opp before leaving */  in armada37xx_cpufreq_driver_init()
524 	while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {  in armada37xx_cpufreq_driver_init()
525 		freq = base_frequency / dvfs->divider[load_lvl];  in armada37xx_cpufreq_driver_init()
538 	struct platform_device *pdev = armada37xx_cpufreq_state->pdev;  in armada37xx_cpufreq_driver_exit()
545 	armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap);  in armada37xx_cpufreq_driver_exit()
548 		freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl];  in armada37xx_cpufreq_driver_exit()
549 		dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq);  in armada37xx_cpufreq_driver_exit()
557 	{ .compatible = "marvell,armada-3700-nb-pm" },
562 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");