Lines Matching +full:interrupt +full:- +full:counter
1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
51 * counter channel.
73 /* Interrupt enable bit in ISR and IER. */
79 #define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */
80 #define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */
81 #define S626_IRQ_COINT2A 0x1000 /* counter 2A overflow interrupt mask */
82 #define S626_IRQ_COINT2B 0x2000 /* counter 2B overflow interrupt mask */
83 #define S626_IRQ_COINT3A 0x4000 /* counter 3A overflow interrupt mask */
84 #define S626_IRQ_COINT3B 0x8000 /* counter 3B overflow interrupt mask */
140 /* Event counter source addresses. */
167 * Event counter 0 threshold
180 * Shut down all MC1-controlled
231 #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
232 #define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */
233 #define S626_P_IER 0x00DC /* Interrupt enable. */
234 #define S626_P_GPIO 0x00E0 /* General-purpose I/O. */
235 #define S626_P_EC1SSR 0x00E4 /* Event counter set 1 source select. */
236 #define S626_P_ECT1R 0x00EC /* Event counter threshold set 1. */
243 #define S626_P_ISR 0x010C /* Interrupt status. */
246 #define S626_P_EC1R 0x0118 /* Event counter set 1. */
273 /* Counter registers (read/write): 0A 1A 2A 0B 1B 2B */
277 /* Counter PreLoad (write) and Latch (read) Registers: 0A 1A 2A 0B 1B 2B */
316 #define S626_A1_SWAP 0x00200000 /* Use big-endian for A1. */
317 #define S626_A2_SWAP 0x00100000 /* Use big-endian for A2. */
320 * WS1-WS4 = CS* outputs.
359 * active-low bits.
385 /* Select parallel-to-serial converter's data source: */
414 * then tri-state.
467 * Enable external interrupt
478 /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */
484 /* 2-bit field that specifies Endian byte lane steering: */
486 * Straight - don't swap any
489 #define S626_DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */
490 #define S626_DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */
493 * 16-bit cycles.
543 #define S626_INTSRC_OVER 1 /* Interrupt on Overflow. */
544 #define S626_INTSRC_INDX 2 /* Interrupt on Index. */
545 #define S626_INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */
564 #define S626_ENCMODE_COUNTER 0 /* Counter mode. */
568 /* Physical CntSrc values (for Counter A source and Counter B source): */
576 * Counter/Extender clock is
580 * Counter/Extender clock is
596 /* Sanity-check limits for parameters. */
599 * Maximum valid counter
612 #define S626_MAKE(x, w, p) (((x) & ((1 << (w)) - 1)) << (p))
613 #define S626_UNMAKE(v, w, p) (((v) >> (p)) & ((1 << (w)) - 1))
617 #define S626_CRABIT_CNTSRC_B 12 /* B counter source. */
621 #define S626_CRABIT_INTSRC_A 5 /* A interrupt source. */
624 #define S626_CRABIT_CNTSRC_A 0 /* A counter source. */
689 #define S626_CRBBIT_INTRESETCMD 15 /* (w) Interrupt reset command. */
690 #define S626_CRBBIT_CNTDIR_B 15 /* (r) B counter direction. */
691 #define S626_CRBBIT_INTRESET_B 14 /* (w) B interrupt reset enable. */
693 #define S626_CRBBIT_INTRESET_A 13 /* (w) A interrupt reset enable. */
696 #define S626_CRBBIT_INTSRC_B 10 /* B interrupt source. */
739 /* Interrupt reset control bits. */