1 /* SPDX-License-Identifier: GPL-2.0+ */
6  * COMEDI - Linux Control and Measurement Device Interface
10  * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 					 * Number of extended-capability
36 #define S626_RANGE_5V		0x10	/* +/-5V range */
37 #define S626_RANGE_10V		0x00	/* +/-10V range */
40 #define S626_GSEL_BIPOLAR5V	0x00F0	/* S626_LP_GSEL setting 5V bipolar. */
41 #define S626_GSEL_BIPOLAR10V	0x00A0	/* S626_LP_GSEL setting 10V bipolar. */
73 /* Interrupt enable bit in ISR and IER. */
180 						 * Shut down all MC1-controlled
231 #define S626_P_RPS0_TOUT	0x00D4	/* RPS0 time-out. */
232 #define S626_P_RPS1_TOUT	0x00D8	/* RPS1 time-out. */
234 #define S626_P_GPIO		0x00E0	/* General-purpose I/O. */
286 /* Bit masks for MISC1 register that are the same for reads and writes. */
289 					 * Watchdog bit).
301 /* Bit masks for MISC1 register reads. */
304 /* Bit masks for MISC2 register writes. */
308 /* Bit masks for MISC2 register that are the same for reads and writes. */
313 /* Bit masks for ACON1 register. */
316 #define S626_A1_SWAP		0x00200000	/* Use big-endian for A1. */
317 #define S626_A2_SWAP		0x00100000	/* Use big-endian for A2. */
320 						 * WS1-WS4 = CS* outputs.
341 /* Bit masks for ACON2 register. */
342 #define S626_A1_CLKSRC_BCLK1	0x00000000	/* A1 bit rate = BCLK1 (ADC). */
344 						 * A2 bit rate = ACLK/1
348 						 * A2 bit rate = ACLK/2
352 						 * A2 bit rate = ACLK/4
359 						 * active-low bits.
366 /* Bit masks for timeslot records. */
385 /* Select parallel-to-serial converter's data source: */
414 						 * then tri-state.
420 						 * I2C bit rate =
424 						 * I2C bus data bit rate
478 /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */
484 /* 2-bit field that specifies Endian byte lane steering: */
486 						 * Straight - don't swap any
489 #define S626_DEBI_CFG_SWAP_2	0x00100000	/* 2-byte swap (Motorola). */
490 #define S626_DEBI_CFG_SWAP_4	0x00200000	/* 4-byte swap. */
493 						 * 16-bit cycles.
556 #define S626_INDXSRC_SOFT	2	/* S/w controlled by IndxPol bit. */
596 /* Sanity-check limits for parameters. */
612 #define S626_MAKE(x, w, p)	(((x) & ((1 << (w)) - 1)) << (p))
613 #define S626_UNMAKE(v, w, p)	(((v) >> (p)) & ((1 << (w)) - 1))  argument
615 /* Bit field positions in CRA: */
626 /* Bit field widths in CRA: */
637 /* Bit field masks for CRA: */
669 #define S626_GET_CRA_INDXSRC_B(v)	\  argument
670 	S626_UNMAKE((v), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B)
671 #define S626_GET_CRA_CNTSRC_B(v)	\  argument
672 	S626_UNMAKE((v), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B)
673 #define S626_GET_CRA_INDXPOL_A(v)	\  argument
674 	S626_UNMAKE((v), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A)
675 #define S626_GET_CRA_LOADSRC_A(v)	\  argument
676 	S626_UNMAKE((v), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A)
677 #define S626_GET_CRA_CLKMULT_A(v)	\  argument
678 	S626_UNMAKE((v), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A)
679 #define S626_GET_CRA_INTSRC_A(v)	\  argument
680 	S626_UNMAKE((v), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A)
681 #define S626_GET_CRA_CLKPOL_A(v)	\  argument
682 	S626_UNMAKE((v), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A)
683 #define S626_GET_CRA_INDXSRC_A(v)	\  argument
684 	S626_UNMAKE((v), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A)
685 #define S626_GET_CRA_CNTSRC_A(v)	\  argument
686 	S626_UNMAKE((v), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A)
688 /* Bit field positions in CRB: */
705 /* Bit field widths in CRB: */
722 /* Bit field masks for CRB: */
771 #define S626_GET_CRB_CNTDIR_B(v)	\  argument
772 	S626_UNMAKE((v), S626_CRBWID_CNTDIR_B, S626_CRBBIT_CNTDIR_B)
773 #define S626_GET_CRB_OVERDO_A(v)	\  argument
774 	S626_UNMAKE((v), S626_CRBWID_OVERDO_A, S626_CRBBIT_OVERDO_A)
775 #define S626_GET_CRB_OVERDO_B(v)	\  argument
776 	S626_UNMAKE((v), S626_CRBWID_OVERDO_B, S626_CRBBIT_OVERDO_B)
777 #define S626_GET_CRB_CLKENAB_A(v)	\  argument
778 	S626_UNMAKE((v), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A)
779 #define S626_GET_CRB_INTSRC_B(v)	\  argument
780 	S626_UNMAKE((v), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B)
781 #define S626_GET_CRB_LATCHSRC(v)	\  argument
782 	S626_UNMAKE((v), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC)
783 #define S626_GET_CRB_LOADSRC_B(v)	\  argument
784 	S626_UNMAKE((v), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B)
785 #define S626_GET_CRB_CLEAR_B(v)	\  argument
786 	S626_UNMAKE((v), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B)
787 #define S626_GET_CRB_CLKMULT_B(v)	\  argument
788 	S626_UNMAKE((v), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B)
789 #define S626_GET_CRB_CLKENAB_B(v)	\  argument
790 	S626_UNMAKE((v), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B)
791 #define S626_GET_CRB_INDXPOL_B(v)	\  argument
792 	S626_UNMAKE((v), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B)
793 #define S626_GET_CRB_CLKPOL_B(v)	\  argument
794 	S626_UNMAKE((v), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B)
796 /* Bit field positions for standardized SETUP structure: */
807 /* Bit field widths for standardized SETUP structure: */
818 /* Bit field masks for standardized SETUP structure: */
850 #define S626_GET_STD_INTSRC(v)	\  argument
851 	S626_UNMAKE((v), S626_STDWID_INTSRC, S626_STDBIT_INTSRC)
852 #define S626_GET_STD_LATCHSRC(v)	\  argument
853 	S626_UNMAKE((v), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC)
854 #define S626_GET_STD_LOADSRC(v)	\  argument
855 	S626_UNMAKE((v), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC)
856 #define S626_GET_STD_INDXSRC(v)	\  argument
857 	S626_UNMAKE((v), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC)
858 #define S626_GET_STD_INDXPOL(v)	\  argument
859 	S626_UNMAKE((v), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL)
860 #define S626_GET_STD_ENCMODE(v)	\  argument
861 	S626_UNMAKE((v), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE)
862 #define S626_GET_STD_CLKPOL(v)	\  argument
863 	S626_UNMAKE((v), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL)
864 #define S626_GET_STD_CLKMULT(v)	\  argument
865 	S626_UNMAKE((v), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT)
866 #define S626_GET_STD_CLKENAB(v)	\  argument
867 	S626_UNMAKE((v), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB)