Lines Matching +full:0 +full:x01400000
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
39 #define S626_EOPL 0x80 /* End of ADC poll list marker. */
40 #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */
41 #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */
44 #define S626_ERR_ILLEGAL_PARM 0x00010000 /*
48 #define S626_ERR_I2C 0x00020000 /* I2C error. */
49 #define S626_ERR_COUNTERSETUP 0x00200000 /*
53 #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */
74 #define S626_IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */
75 #define S626_IRQ_RPS1 0x10000000
76 #define S626_ISR_AFOU 0x00000800
79 #define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */
80 #define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */
81 #define S626_IRQ_COINT2A 0x1000 /* counter 2A overflow interrupt mask */
82 #define S626_IRQ_COINT2B 0x2000 /* counter 2B overflow interrupt mask */
83 #define S626_IRQ_COINT3A 0x4000 /* counter 3A overflow interrupt mask */
84 #define S626_IRQ_COINT3B 0x8000 /* counter 3B overflow interrupt mask */
87 #define S626_RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */
88 #define S626_RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */
89 #define S626_RPS_NOP 0x00000000 /* NOP */
90 #define S626_RPS_PAUSE 0x20000000 /* PAUSE */
91 #define S626_RPS_UPLOAD 0x40000000 /* UPLOAD */
92 #define S626_RPS_JUMP 0x80000000 /* JUMP */
93 #define S626_RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */
94 #define S626_RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */
95 #define S626_RPS_STOP 0x50000000 /* STOP */
96 #define S626_RPS_IRQ 0x60000000 /* IRQ */
98 #define S626_RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */
99 #define S626_RPS_INVERT 0x04000000 /*
103 #define S626_RPS_DEBI 0x00000002 /* DEBI done */
105 #define S626_RPS_SIG0 0x00200000 /*
106 * RPS semaphore 0
109 #define S626_RPS_SIG1 0x00400000 /*
113 #define S626_RPS_SIG2 0x00800000 /*
117 #define S626_RPS_GPIO2 0x00080000 /* RPS GPIO2 */
118 #define S626_RPS_GPIO3 0x00100000 /* RPS GPIO3 */
141 #define S626_SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */
144 #define S626_GPIO_BASE 0x10004000 /*
145 * GPIO 0,2,3 = inputs,
148 #define S626_GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */
149 #define S626_GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */
152 #define S626_PSR_DEBI_E 0x00040000 /* DEBI event flag. */
153 #define S626_PSR_DEBI_S 0x00080000 /* DEBI status flag. */
154 #define S626_PSR_A2_IN 0x00008000 /*
158 #define S626_PSR_AFOU 0x00000800 /*
162 #define S626_PSR_GPIO2 0x00000020 /*
163 * GPIO2 input pin: 0=AdcBusy,
166 #define S626_PSR_EC0S 0x00000001 /*
167 * Event counter 0 threshold
172 #define S626_SSR_AF2_OUT 0x00000200 /*
178 #define S626_MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */
179 #define S626_MC1_SHUTDOWN 0x3FFF0000 /*
184 #define S626_MC1_ERPS1 0x2000 /* Enab/disable RPS task 1. */
185 #define S626_MC1_ERPS0 0x1000 /* Enab/disable RPS task 0. */
186 #define S626_MC1_DEBI 0x0800 /* Enab/disable DEBI pins. */
187 #define S626_MC1_AUDIO 0x0200 /* Enab/disable audio port pins. */
188 #define S626_MC1_I2C 0x0100 /* Enab/disable I2C interface. */
189 #define S626_MC1_A2OUT 0x0008 /* Enab/disable transfer on A2 out. */
190 #define S626_MC1_A2IN 0x0004 /* Enab/disable transfer on A2 in. */
191 #define S626_MC1_A1IN 0x0001 /* Enab/disable transfer on A1 in. */
194 #define S626_MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */
195 #define S626_MC2_UPLD_IIC 0x0001 /* Upload I2C. */
196 #define S626_MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */
197 #define S626_MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */
198 #define S626_MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */
204 #define S626_P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */
205 #define S626_P_DEBICFG 0x007C /* DEBI configuration. */
206 #define S626_P_DEBICMD 0x0080 /* DEBI command. */
207 #define S626_P_DEBIPAGE 0x0084 /* DEBI page. */
208 #define S626_P_DEBIAD 0x0088 /* DEBI target address. */
209 #define S626_P_I2CCTRL 0x008C /* I2C control. */
210 #define S626_P_I2CSTAT 0x0090 /* I2C status. */
211 #define S626_P_BASEA2_IN 0x00AC /*
215 #define S626_P_PROTA2_IN 0x00B0 /*
219 #define S626_P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */
220 #define S626_P_BASEA2_OUT 0x00B8 /*
224 #define S626_P_PROTA2_OUT 0x00BC /*
228 #define S626_P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */
229 #define S626_P_RPSPAGE0 0x00C4 /* RPS0 page. */
230 #define S626_P_RPSPAGE1 0x00C8 /* RPS1 page. */
231 #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
232 #define S626_P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */
233 #define S626_P_IER 0x00DC /* Interrupt enable. */
234 #define S626_P_GPIO 0x00E0 /* General-purpose I/O. */
235 #define S626_P_EC1SSR 0x00E4 /* Event counter set 1 source select. */
236 #define S626_P_ECT1R 0x00EC /* Event counter threshold set 1. */
237 #define S626_P_ACON1 0x00F4 /* Audio control 1. */
238 #define S626_P_ACON2 0x00F8 /* Audio control 2. */
239 #define S626_P_MC1 0x00FC /* Master control 1. */
240 #define S626_P_MC2 0x0100 /* Master control 2. */
241 #define S626_P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */
242 #define S626_P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */
243 #define S626_P_ISR 0x010C /* Interrupt status. */
244 #define S626_P_PSR 0x0110 /* Primary status. */
245 #define S626_P_SSR 0x0114 /* Secondary status. */
246 #define S626_P_EC1R 0x0118 /* Event counter set 1. */
247 #define S626_P_ADP4 0x0138 /*
251 #define S626_P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */
252 #define S626_P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */
253 #define S626_P_TSL1 0x0180 /* Audio time slot list 1. */
254 #define S626_P_TSL2 0x01C0 /* Audio time slot list 2. */
258 #define S626_LP_DACPOL 0x0082 /* Write DAC polarity. */
259 #define S626_LP_GSEL 0x0084 /* Write ADC gain. */
260 #define S626_LP_ISEL 0x0086 /* Write ADC channel select. */
263 #define S626_LP_RDDIN(x) (0x0040 + (x) * 0x10) /* R: digital input */
264 #define S626_LP_WRINTSEL(x) (0x0042 + (x) * 0x10) /* W: int enable */
265 #define S626_LP_WREDGSEL(x) (0x0044 + (x) * 0x10) /* W: edge selection */
266 #define S626_LP_WRCAPSEL(x) (0x0046 + (x) * 0x10) /* W: capture enable */
267 #define S626_LP_RDCAPFLG(x) (0x0048 + (x) * 0x10) /* R: edges captured */
268 #define S626_LP_WRDOUT(x) (0x0048 + (x) * 0x10) /* W: digital output */
269 #define S626_LP_RDINTSEL(x) (0x004a + (x) * 0x10) /* R: int enable */
270 #define S626_LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */
271 #define S626_LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */
273 /* Counter registers (read/write): 0A 1A 2A 0B 1B 2B */
274 #define S626_LP_CRA(x) (0x0000 + (((x) % 3) * 0x4))
275 #define S626_LP_CRB(x) (0x0002 + (((x) % 3) * 0x4))
277 /* Counter PreLoad (write) and Latch (read) Registers: 0A 1A 2A 0B 1B 2B */
278 #define S626_LP_CNTR(x) (0x000c + (((x) < 3) ? 0x0 : 0x4) + \
279 (((x) % 3) * 0x8))
282 #define S626_LP_MISC1 0x0088 /* Read/write Misc1. */
283 #define S626_LP_WRMISC2 0x0090 /* Write Misc2. */
284 #define S626_LP_RDMISC2 0x0082 /* Read Misc2. */
287 #define S626_MISC1_WENABLE 0x8000 /*
291 #define S626_MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */
292 #define S626_MISC1_EDCAP 0x1000 /*
296 #define S626_MISC1_NOEDCAP 0x0000 /*
302 #define S626_RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */
305 #define S626_WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */
306 #define S626_WRMISC2_CHARGE_ENABLE 0x4000 /* Enable battery trickle charging. */
309 #define S626_MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */
310 #define S626_MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */
311 #define S626_MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval select mask. */
314 #define S626_A2_RUN 0x40000000 /* Run A2 based on TSL2. */
315 #define S626_A1_RUN 0x20000000 /* Run A1 based on TSL1. */
316 #define S626_A1_SWAP 0x00200000 /* Use big-endian for A1. */
317 #define S626_A2_SWAP 0x00100000 /* Use big-endian for A2. */
318 #define S626_WS_MODES 0x00019999 /*
342 #define S626_A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */
343 #define S626_A2_CLKSRC_X1 0x00800000 /*
347 #define S626_A2_CLKSRC_X2 0x00C00000 /*
351 #define S626_A2_CLKSRC_X4 0x01400000 /*
355 #define S626_INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */
356 #define S626_BCLK2_OE 0x00040000 /* Enable BCLK2 (DACs). */
357 #define S626_ACON2_XORMASK 0x000C0000 /*
367 #define S626_WS1 0x40000000 /* WS output to assert. */
368 #define S626_WS2 0x20000000
369 #define S626_WS3 0x10000000
370 #define S626_WS4 0x08000000
371 #define S626_RSD1 0x01000000 /* Shift A1 data in on SD1. */
372 #define S626_SDW_A1 0x00800000 /*
376 #define S626_SIB_A1 0x00400000 /*
380 #define S626_SF_A1 0x00200000 /*
386 #define S626_XFIFO_0 0x00000000 /* Data fifo byte 0. */
387 #define S626_XFIFO_1 0x00000010 /* Data fifo byte 1. */
388 #define S626_XFIFO_2 0x00000020 /* Data fifo byte 2. */
389 #define S626_XFIFO_3 0x00000030 /* Data fifo byte 3. */
390 #define S626_XFB0 0x00000040 /* FB_BUFFER byte 0. */
391 #define S626_XFB1 0x00000050 /* FB_BUFFER byte 1. */
392 #define S626_XFB2 0x00000060 /* FB_BUFFER byte 2. */
393 #define S626_XFB3 0x00000070 /* FB_BUFFER byte 3. */
394 #define S626_SIB_A2 0x00000200 /*
399 #define S626_SF_A2 0x00000100 /*
404 #define S626_LF_A2 0x00000080 /*
409 #define S626_XSD2 0x00000008 /* Shift data out on SD2. */
410 #define S626_RSD3 0x00001800 /* Shift data in on SD3. */
411 #define S626_RSD2 0x00001000 /* Shift data in on SD2. */
412 #define S626_LOW_A2 0x00000002 /*
416 #define S626_EOS 0x00000001 /* End of superframe. */
419 #define S626_I2C_CLKSEL 0x0400 /*
438 #define S626_I2C_ERR 0x0002 /* I2C control/status flag ERROR. */
439 #define S626_I2C_BUSY 0x0001 /* I2C control/status flag BUSY. */
440 #define S626_I2C_ABORT 0x0080 /* I2C status flag ABORT. */
441 #define S626_I2C_ATTRSTART 0x3 /* I2C attribute START. */
442 #define S626_I2C_ATTRCONT 0x2 /* I2C attribute CONT. */
443 #define S626_I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */
444 #define S626_I2C_ATTRNOP 0x0 /* I2C attribute NOP. */
456 #define S626_DEBI_CMD_READ 0x00010000 /* Read operation. */
457 #define S626_DEBI_CMD_WRITE 0x00000000 /* Write operation. */
466 #define S626_DEBI_CFG_XIRQ_EN 0x80000000 /*
470 #define S626_DEBI_CFG_XRESUME 0x40000000 /* Resume block */
475 #define S626_DEBI_CFG_TOQ 0x03C00000 /* Timeout (15 PCI cycles). */
476 #define S626_DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */
485 #define S626_DEBI_CFG_SWAP_NONE 0x00000000 /*
489 #define S626_DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */
490 #define S626_DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */
491 #define S626_DEBI_CFG_SLAVE16 0x00080000 /*
495 #define S626_DEBI_CFG_INC 0x00040000 /*
499 #define S626_DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */
500 #define S626_DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */
525 #define S626_DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */
530 #define S626_LOADSRC_INDX 0 /* Preload core in response to Index. */
542 #define S626_INTSRC_NONE 0 /* Interrupts disabled. */
548 #define S626_LATCHSRC_AB_READ 0 /* Latch on read. */
554 #define S626_INDXSRC_ENCODER 0 /* Encoder. */
560 #define S626_INDXPOL_POS 0 /* Index input is active high. */
564 #define S626_ENCMODE_COUNTER 0 /* Counter mode. */
569 #define S626_CNTSRC_ENCODER 0 /* Encoder */
575 #define S626_CLKPOL_POS 0 /*
583 #define S626_CNTDIR_UP 0 /* Timer counts up. */
587 #define S626_CLKENAB_ALWAYS 0 /* Clock always enabled. */
591 #define S626_CLKMULT_4X 0 /* 4x clock multiplier. */
624 #define S626_CRABIT_CNTSRC_A 0 /* A counter source. */
638 #define S626_CRAMSK_INDXSRC_B S626_SET_CRA_INDXSRC_B(~0)
639 #define S626_CRAMSK_CNTSRC_B S626_SET_CRA_CNTSRC_B(~0)
640 #define S626_CRAMSK_INDXPOL_A S626_SET_CRA_INDXPOL_A(~0)
641 #define S626_CRAMSK_LOADSRC_A S626_SET_CRA_LOADSRC_A(~0)
642 #define S626_CRAMSK_CLKMULT_A S626_SET_CRA_CLKMULT_A(~0)
643 #define S626_CRAMSK_INTSRC_A S626_SET_CRA_INTSRC_A(~0)
644 #define S626_CRAMSK_CLKPOL_A S626_SET_CRA_CLKPOL_A(~0)
645 #define S626_CRAMSK_INDXSRC_A S626_SET_CRA_INDXSRC_A(~0)
646 #define S626_CRAMSK_CNTSRC_A S626_SET_CRA_CNTSRC_A(~0)
703 #define S626_CRBBIT_CLKPOL_B 0 /* B clock polarity. */
723 #define S626_CRBMSK_INTRESETCMD S626_SET_CRB_INTRESETCMD(~0) /* (w) */
725 #define S626_CRBMSK_INTRESET_B S626_SET_CRB_INTRESET_B(~0) /* (w) */
727 #define S626_CRBMSK_INTRESET_A S626_SET_CRB_INTRESET_A(~0) /* (w) */
729 #define S626_CRBMSK_CLKENAB_A S626_SET_CRB_CLKENAB_A(~0)
730 #define S626_CRBMSK_INTSRC_B S626_SET_CRB_INTSRC_B(~0)
731 #define S626_CRBMSK_LATCHSRC S626_SET_CRB_LATCHSRC(~0)
732 #define S626_CRBMSK_LOADSRC_B S626_SET_CRB_LOADSRC_B(~0)
733 #define S626_CRBMSK_CLEAR_B S626_SET_CRB_CLEAR_B(~0)
734 #define S626_CRBMSK_CLKMULT_B S626_SET_CRB_CLKMULT_B(~0)
735 #define S626_CRBMSK_CLKENAB_B S626_SET_CRB_CLKENAB_B(~0)
736 #define S626_CRBMSK_INDXPOL_B S626_SET_CRB_INDXPOL_B(~0)
737 #define S626_CRBMSK_CLKPOL_B S626_SET_CRB_CLKPOL_B(~0)
805 #define S626_STDBIT_CLKENAB 0
819 #define S626_STDMSK_INTSRC S626_SET_STD_INTSRC(~0)
820 #define S626_STDMSK_LATCHSRC S626_SET_STD_LATCHSRC(~0)
821 #define S626_STDMSK_LOADSRC S626_SET_STD_LOADSRC(~0)
822 #define S626_STDMSK_INDXSRC S626_SET_STD_INDXSRC(~0)
823 #define S626_STDMSK_INDXPOL S626_SET_STD_INDXPOL(~0)
824 #define S626_STDMSK_ENCMODE S626_SET_STD_ENCMODE(~0)
825 #define S626_STDMSK_CLKPOL S626_SET_STD_CLKPOL(~0)
826 #define S626_STDMSK_CLKMULT S626_SET_STD_CLKMULT(~0)
827 #define S626_STDMSK_CLKENAB S626_SET_STD_CLKENAB(~0)