Lines Matching +full:v +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
23 * It has 16 single-ended or 8 differential Analogue Input channels with
24 * 12-bit resolution. Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.
28 * There are 4 x 12-bit Analogue Outputs. Ranges : 5V, 10V, +/-5V, +/-10V
30 * 16 x Digital Inputs, 24V
32 * 8 x Digital Outputs, 24V, 1A
34 * 4 x 16-bit counters - not implemented
42 #define ICP_MULTI_ADC_CSR_ST BIT(0) /* Start ADC */
43 #define ICP_MULTI_ADC_CSR_BSY BIT(0) /* ADC busy */
44 #define ICP_MULTI_ADC_CSR_BI BIT(4) /* Bipolar input range */
45 #define ICP_MULTI_ADC_CSR_RA BIT(5) /* Input range 0 = 5V, 1 = 10V */
46 #define ICP_MULTI_ADC_CSR_DI BIT(6) /* Input mode 1 = differential */
51 #define ICP_MULTI_DAC_CSR_ST BIT(0) /* Start DAC */
52 #define ICP_MULTI_DAC_CSR_BSY BIT(0) /* DAC busy */
53 #define ICP_MULTI_DAC_CSR_BI BIT(4) /* Bipolar output range */
54 #define ICP_MULTI_DAC_CSR_RA BIT(5) /* Output range 0 = 5V, 1 = 10V */
61 #define ICP_MULTI_INT_ADC_RDY BIT(0) /* A/D conversion ready interrupt */
62 #define ICP_MULTI_INT_DAC_RDY BIT(1) /* D/A conversion ready interrupt */
63 #define ICP_MULTI_INT_DOUT_ERR BIT(2) /* Digital output error interrupt */
64 #define ICP_MULTI_INT_DIN_STAT BIT(3) /* Digital input status change int. */
65 #define ICP_MULTI_INT_CIE0 BIT(4) /* Counter 0 overrun interrupt */
66 #define ICP_MULTI_INT_CIE1 BIT(5) /* Counter 1 overrun interrupt */
67 #define ICP_MULTI_INT_CIE2 BIT(6) /* Counter 2 overrun interrupt */
68 #define ICP_MULTI_INT_CIE3 BIT(7) /* Counter 3 overrun interrupt */
94 status = readw(dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_eoc()
97 return -EBUSY; in icp_multi_ai_eoc()
105 unsigned int chan = CR_CHAN(insn->chanspec); in icp_multi_ai_insn_read()
106 unsigned int range = CR_RANGE(insn->chanspec); in icp_multi_ai_insn_read()
107 unsigned int aref = CR_AREF(insn->chanspec); in icp_multi_ai_insn_read()
120 writew(adc_csr, dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_insn_read()
122 for (n = 0; n < insn->n; n++) { in icp_multi_ai_insn_read()
123 /* Set start ADC bit */ in icp_multi_ai_insn_read()
125 dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_insn_read()
134 data[n] = (readw(dev->mmio + ICP_MULTI_AI) >> 4) & 0x0fff; in icp_multi_ai_insn_read()
147 status = readw(dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_ready()
150 return -EBUSY; in icp_multi_ao_ready()
158 unsigned int chan = CR_CHAN(insn->chanspec); in icp_multi_ao_insn_write()
159 unsigned int range = CR_RANGE(insn->chanspec); in icp_multi_ao_insn_write()
166 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_insn_write()
168 for (i = 0; i < insn->n; i++) { in icp_multi_ao_insn_write()
177 writew(val, dev->mmio + ICP_MULTI_AO); in icp_multi_ao_insn_write()
179 /* Set start conversion bit to write data to channel */ in icp_multi_ao_insn_write()
181 dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_insn_write()
183 s->readback[chan] = val; in icp_multi_ao_insn_write()
186 return insn->n; in icp_multi_ao_insn_write()
194 data[1] = readw(dev->mmio + ICP_MULTI_DI); in icp_multi_di_insn_bits()
196 return insn->n; in icp_multi_di_insn_bits()
205 writew(s->state, dev->mmio + ICP_MULTI_DO); in icp_multi_do_insn_bits()
207 data[1] = s->state; in icp_multi_do_insn_bits()
209 return insn->n; in icp_multi_do_insn_bits()
217 writew(0, dev->mmio + ICP_MULTI_INT_EN); in icp_multi_reset()
218 writew(ICP_MULTI_INT_MASK, dev->mmio + ICP_MULTI_INT_STAT); in icp_multi_reset()
220 /* Reset the analog output channels to 0V */ in icp_multi_reset()
224 /* Select channel and 0..5V range */ in icp_multi_reset()
225 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_reset()
227 /* Output 0V */ in icp_multi_reset()
228 writew(0, dev->mmio + ICP_MULTI_AO); in icp_multi_reset()
230 /* Set start conversion bit to write data to channel */ in icp_multi_reset()
232 dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_reset()
237 writew(0, dev->mmio + ICP_MULTI_DO); in icp_multi_reset()
253 dev->mmio = pci_ioremap_bar(pcidev, 2); in icp_multi_auto_attach()
254 if (!dev->mmio) in icp_multi_auto_attach()
255 return -ENOMEM; in icp_multi_auto_attach()
264 s = &dev->subdevices[0]; in icp_multi_auto_attach()
265 s->type = COMEDI_SUBD_AI; in icp_multi_auto_attach()
266 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF; in icp_multi_auto_attach()
267 s->n_chan = 16; in icp_multi_auto_attach()
268 s->maxdata = 0x0fff; in icp_multi_auto_attach()
269 s->range_table = &icp_multi_ranges; in icp_multi_auto_attach()
270 s->insn_read = icp_multi_ai_insn_read; in icp_multi_auto_attach()
273 s = &dev->subdevices[1]; in icp_multi_auto_attach()
274 s->type = COMEDI_SUBD_AO; in icp_multi_auto_attach()
275 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON; in icp_multi_auto_attach()
276 s->n_chan = 4; in icp_multi_auto_attach()
277 s->maxdata = 0x0fff; in icp_multi_auto_attach()
278 s->range_table = &icp_multi_ranges; in icp_multi_auto_attach()
279 s->insn_write = icp_multi_ao_insn_write; in icp_multi_auto_attach()
286 s = &dev->subdevices[2]; in icp_multi_auto_attach()
287 s->type = COMEDI_SUBD_DI; in icp_multi_auto_attach()
288 s->subdev_flags = SDF_READABLE; in icp_multi_auto_attach()
289 s->n_chan = 16; in icp_multi_auto_attach()
290 s->maxdata = 1; in icp_multi_auto_attach()
291 s->range_table = &range_digital; in icp_multi_auto_attach()
292 s->insn_bits = icp_multi_di_insn_bits; in icp_multi_auto_attach()
295 s = &dev->subdevices[3]; in icp_multi_auto_attach()
296 s->type = COMEDI_SUBD_DO; in icp_multi_auto_attach()
297 s->subdev_flags = SDF_WRITABLE; in icp_multi_auto_attach()
298 s->n_chan = 8; in icp_multi_auto_attach()
299 s->maxdata = 1; in icp_multi_auto_attach()
300 s->range_table = &range_digital; in icp_multi_auto_attach()
301 s->insn_bits = icp_multi_do_insn_bits; in icp_multi_auto_attach()
316 return comedi_pci_auto_config(dev, &icp_multi_driver, id->driver_data); in icp_multi_pci_probe()