69 #define SYST_CON_REG(to)        (timer_of_base(to) + SYST_CON)
70 #define SYST_VAL_REG(to)        (timer_of_base(to) + SYST_VAL)
90 	writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);  in mtk_cpux_readl()
91 	return readl(timer_of_base(to) + CPUX_CON_REG);  in mtk_cpux_readl()
96 	writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);  in mtk_cpux_writel()
97 	writel(val, timer_of_base(to) + CPUX_CON_REG);  in mtk_cpux_writel()
202 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_stop()
203 	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +  in mtk_gpt_clkevt_time_stop()
210 	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));  in mtk_gpt_clkevt_time_setup()
219 	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_clkevt_time_start()
221 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_start()
232 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_clkevt_time_start()
271 	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_interrupt()
281 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_setup()
284 	       timer_of_base(to) + GPT_CLK_REG(timer));  in mtk_gpt_setup()
286 	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));  in mtk_gpt_setup()
289 	       timer_of_base(to) + GPT_CTRL_REG(timer));  in mtk_gpt_setup()
297 	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
300 	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_enable_irq()
302 	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
304 	       timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_enable_irq()
319 	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);  in mtk_gpt_suspend()
326 	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);  in mtk_gpt_suspend()
438 	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),  in mtk_gpt_init()
441 	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);  in mtk_gpt_init()