91 	struct sh_cmt_device *cmt;  member
243 		return ch->cmt->info->read_control(ch->iostart, 0);  in sh_cmt_read_cmstr()
245 		return ch->cmt->info->read_control(ch->cmt->mapbase, 0);  in sh_cmt_read_cmstr()
251 		ch->cmt->info->write_control(ch->iostart, 0, value);  in sh_cmt_write_cmstr()
253 		ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);  in sh_cmt_write_cmstr()
258 	return ch->cmt->info->read_control(ch->ioctrl, CMCSR);  in sh_cmt_read_cmcsr()
263 	ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);  in sh_cmt_write_cmcsr()
268 	return ch->cmt->info->read_count(ch->ioctrl, CMCNT);  in sh_cmt_read_cmcnt()
273 	ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);  in sh_cmt_write_cmcnt()
278 	ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);  in sh_cmt_write_cmcor()
286 	o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;  in sh_cmt_get_counter()
294 		o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;  in sh_cmt_get_counter()
308 	raw_spin_lock_irqsave(&ch->cmt->lock, flags);  in sh_cmt_start_stop_ch()
317 	raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);  in sh_cmt_start_stop_ch()
324 	dev_pm_syscore_device(&ch->cmt->pdev->dev, true);  in sh_cmt_enable()
327 	ret = clk_enable(ch->cmt->clk);  in sh_cmt_enable()
329 		dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",  in sh_cmt_enable()
338 	if (ch->cmt->info->width == 16) {  in sh_cmt_enable()
342 		u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ?  in sh_cmt_enable()
370 		dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",  in sh_cmt_enable()
381 	clk_disable(ch->cmt->clk);  in sh_cmt_enable()
396 	clk_disable(ch->cmt->clk);  in sh_cmt_disable()
398 	dev_pm_syscore_device(&ch->cmt->pdev->dev, false);  in sh_cmt_disable()
488 			dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",  in sh_cmt_clock_event_program_verify()
497 		dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",  in __sh_cmt_set_next()
519 			   ch->cmt->info->clear_bits);  in sh_cmt_interrupt()
567 		pm_runtime_get_sync(&ch->cmt->pdev->dev);  in sh_cmt_start()
573 			pm_runtime_get_sync(&ch->cmt->pdev->dev);  in sh_cmt_start()
582 	if (ch->cmt->num_channels == 1 &&  in sh_cmt_start()
604 			pm_runtime_put(&ch->cmt->pdev->dev);  in sh_cmt_stop()
614 		pm_runtime_put(&ch->cmt->pdev->dev);  in sh_cmt_stop()
627 	if (ch->cmt->num_channels == 1) {  in sh_cmt_clocksource_read()
680 	dev_pm_genpd_suspend(&ch->cmt->pdev->dev);  in sh_cmt_clocksource_suspend()
690 	dev_pm_genpd_resume(&ch->cmt->pdev->dev);  in sh_cmt_clocksource_resume()
706 	cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);  in sh_cmt_register_clocksource()
709 	dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",  in sh_cmt_register_clocksource()
712 	clocksource_register_hz(cs, ch->cmt->rate);  in sh_cmt_register_clocksource()
726 		sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);  in sh_cmt_clock_event_start()
748 	dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",  in sh_cmt_clock_event_set_state()
782 	dev_pm_genpd_suspend(&ch->cmt->pdev->dev);  in sh_cmt_clock_event_suspend()
783 	clk_unprepare(ch->cmt->clk);  in sh_cmt_clock_event_suspend()
790 	clk_prepare(ch->cmt->clk);  in sh_cmt_clock_event_resume()
791 	dev_pm_genpd_resume(&ch->cmt->pdev->dev);  in sh_cmt_clock_event_resume()
801 	irq = platform_get_irq(ch->cmt->pdev, ch->index);  in sh_cmt_register_clockevent()
807 			  dev_name(&ch->cmt->pdev->dev), ch);  in sh_cmt_register_clockevent()
809 		dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_cmt_register_clockevent()
828 	ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);  in sh_cmt_register_clockevent()
834 	dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",  in sh_cmt_register_clockevent()
847 		ch->cmt->has_clockevent = true;  in sh_cmt_register()
854 		ch->cmt->has_clocksource = true;  in sh_cmt_register()
863 				bool clocksource, struct sh_cmt_device *cmt)  in sh_cmt_setup_channel()  argument
872 	ch->cmt = cmt;  in sh_cmt_setup_channel()
882 	switch (cmt->info->model) {  in sh_cmt_setup_channel()
884 		ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;  in sh_cmt_setup_channel()
888 		ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;  in sh_cmt_setup_channel()
892 		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;  in sh_cmt_setup_channel()
897 		value = ioread32(cmt->mapbase + CMCLKE);  in sh_cmt_setup_channel()
899 		iowrite32(value, cmt->mapbase + CMCLKE);  in sh_cmt_setup_channel()
903 	if (cmt->info->width == (sizeof(ch->max_match_value) * 8))  in sh_cmt_setup_channel()
906 		ch->max_match_value = (1 << cmt->info->width) - 1;  in sh_cmt_setup_channel()
911 	ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),  in sh_cmt_setup_channel()
914 		dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",  in sh_cmt_setup_channel()
923 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)  in sh_cmt_map_memory()  argument
927 	mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);  in sh_cmt_map_memory()
929 		dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");  in sh_cmt_map_memory()
933 	cmt->mapbase = ioremap(mem->start, resource_size(mem));  in sh_cmt_map_memory()
934 	if (cmt->mapbase == NULL) {  in sh_cmt_map_memory()
935 		dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");  in sh_cmt_map_memory()
996 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)  in sh_cmt_setup()  argument
1002 	cmt->pdev = pdev;  in sh_cmt_setup()
1003 	raw_spin_lock_init(&cmt->lock);  in sh_cmt_setup()
1006 		cmt->info = of_device_get_match_data(&pdev->dev);  in sh_cmt_setup()
1007 		cmt->hw_channels = cmt->info->channels_mask;  in sh_cmt_setup()
1012 		cmt->info = (const struct sh_cmt_info *)id->driver_data;  in sh_cmt_setup()
1013 		cmt->hw_channels = cfg->channels_mask;  in sh_cmt_setup()
1015 		dev_err(&cmt->pdev->dev, "missing platform data\n");  in sh_cmt_setup()
1020 	cmt->clk = clk_get(&cmt->pdev->dev, "fck");  in sh_cmt_setup()
1021 	if (IS_ERR(cmt->clk)) {  in sh_cmt_setup()
1022 		dev_err(&cmt->pdev->dev, "cannot get clock\n");  in sh_cmt_setup()
1023 		return PTR_ERR(cmt->clk);  in sh_cmt_setup()
1026 	ret = clk_prepare(cmt->clk);  in sh_cmt_setup()
1031 	ret = clk_enable(cmt->clk);  in sh_cmt_setup()
1035 	if (cmt->info->width == 16)  in sh_cmt_setup()
1036 		cmt->rate = clk_get_rate(cmt->clk) / 512;  in sh_cmt_setup()
1038 		cmt->rate = clk_get_rate(cmt->clk) / 8;  in sh_cmt_setup()
1041 	ret = sh_cmt_map_memory(cmt);  in sh_cmt_setup()
1046 	cmt->num_channels = hweight8(cmt->hw_channels);  in sh_cmt_setup()
1047 	cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),  in sh_cmt_setup()
1049 	if (cmt->channels == NULL) {  in sh_cmt_setup()
1058 	for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {  in sh_cmt_setup()
1060 		bool clocksource = i == 1 || cmt->num_channels == 1;  in sh_cmt_setup()
1063 		ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,  in sh_cmt_setup()
1064 					   clockevent, clocksource, cmt);  in sh_cmt_setup()
1071 	clk_disable(cmt->clk);  in sh_cmt_setup()
1073 	platform_set_drvdata(pdev, cmt);  in sh_cmt_setup()
1078 	kfree(cmt->channels);  in sh_cmt_setup()
1079 	iounmap(cmt->mapbase);  in sh_cmt_setup()
1081 	clk_disable(cmt->clk);  in sh_cmt_setup()
1083 	clk_unprepare(cmt->clk);  in sh_cmt_setup()
1085 	clk_put(cmt->clk);  in sh_cmt_setup()
1091 	struct sh_cmt_device *cmt = platform_get_drvdata(pdev);  in sh_cmt_probe()  local
1099 	if (cmt) {  in sh_cmt_probe()
1104 	cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);  in sh_cmt_probe()
1105 	if (cmt == NULL)  in sh_cmt_probe()
1108 	ret = sh_cmt_setup(cmt, pdev);  in sh_cmt_probe()
1110 		kfree(cmt);  in sh_cmt_probe()
1118 	if (cmt->has_clockevent || cmt->has_clocksource)  in sh_cmt_probe()