Lines Matching +full:rcar +full:- +full:gen2 +full:- +full:can
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
238 #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */
242 if (ch->iostart) in sh_cmt_read_cmstr()
243 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
245 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
250 if (ch->iostart) in sh_cmt_write_cmstr()
251 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
253 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
258 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); in sh_cmt_read_cmcsr()
263 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); in sh_cmt_write_cmcsr()
268 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); in sh_cmt_read_cmcnt()
273 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); in sh_cmt_write_cmcnt()
278 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); in sh_cmt_write_cmcor()
286 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
294 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
308 raw_spin_lock_irqsave(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
312 value |= 1 << ch->timer_bit; in sh_cmt_start_stop_ch()
314 value &= ~(1 << ch->timer_bit); in sh_cmt_start_stop_ch()
317 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
324 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); in sh_cmt_enable()
327 ret = clk_enable(ch->cmt->clk); in sh_cmt_enable()
329 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", in sh_cmt_enable()
330 ch->index); in sh_cmt_enable()
338 if (ch->cmt->info->width == 16) { in sh_cmt_enable()
342 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? in sh_cmt_enable()
353 * According to the sh73a0 user's manual, as CMCNT can be operated in sh_cmt_enable()
370 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", in sh_cmt_enable()
371 ch->index); in sh_cmt_enable()
372 ret = -ETIMEDOUT; in sh_cmt_enable()
381 clk_disable(ch->cmt->clk); in sh_cmt_enable()
396 clk_disable(ch->cmt->clk); in sh_cmt_disable()
398 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); in sh_cmt_disable()
411 u32 value = ch->next_match_value; in sh_cmt_clock_event_program_verify()
418 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ in sh_cmt_clock_event_program_verify()
422 * -> let the interrupt handler reprogram the timer. in sh_cmt_clock_event_program_verify()
423 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
425 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
437 if (new_match > ch->max_match_value) in sh_cmt_clock_event_program_verify()
438 new_match = ch->max_match_value; in sh_cmt_clock_event_program_verify()
443 if (has_wrapped && (new_match > ch->match_value)) { in sh_cmt_clock_event_program_verify()
447 * -> first interrupt reprograms the timer. in sh_cmt_clock_event_program_verify()
448 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
450 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
458 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
459 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
461 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
469 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
470 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
472 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
480 * -> increase delay and retry. in sh_cmt_clock_event_program_verify()
488 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", in sh_cmt_clock_event_program_verify()
489 ch->index); in sh_cmt_clock_event_program_verify()
496 if (delta > ch->max_match_value) in __sh_cmt_set_next()
497 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", in __sh_cmt_set_next()
498 ch->index); in __sh_cmt_set_next()
500 ch->next_match_value = delta; in __sh_cmt_set_next()
508 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_set_next()
510 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_set_next()
519 ch->cmt->info->clear_bits); in sh_cmt_interrupt()
525 if (ch->flags & FLAG_CLOCKSOURCE) in sh_cmt_interrupt()
526 ch->total_cycles += ch->match_value + 1; in sh_cmt_interrupt()
528 if (!(ch->flags & FLAG_REPROGRAM)) in sh_cmt_interrupt()
529 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
531 ch->flags |= FLAG_IRQCONTEXT; in sh_cmt_interrupt()
533 if (ch->flags & FLAG_CLOCKEVENT) { in sh_cmt_interrupt()
534 if (!(ch->flags & FLAG_SKIPEVENT)) { in sh_cmt_interrupt()
535 if (clockevent_state_oneshot(&ch->ced)) { in sh_cmt_interrupt()
536 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
537 ch->flags |= FLAG_REPROGRAM; in sh_cmt_interrupt()
540 ch->ced.event_handler(&ch->ced); in sh_cmt_interrupt()
544 ch->flags &= ~FLAG_SKIPEVENT; in sh_cmt_interrupt()
546 if (ch->flags & FLAG_REPROGRAM) { in sh_cmt_interrupt()
547 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
550 if (ch->flags & FLAG_CLOCKEVENT) in sh_cmt_interrupt()
551 if ((clockevent_state_shutdown(&ch->ced)) in sh_cmt_interrupt()
552 || (ch->match_value == ch->next_match_value)) in sh_cmt_interrupt()
553 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
556 ch->flags &= ~FLAG_IRQCONTEXT; in sh_cmt_interrupt()
567 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_start()
569 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_start()
571 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { in sh_cmt_start()
573 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_start()
579 ch->flags |= flag; in sh_cmt_start()
582 if (ch->cmt->num_channels == 1 && in sh_cmt_start()
583 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) in sh_cmt_start()
584 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_start()
586 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_start()
596 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_stop()
598 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); in sh_cmt_stop()
599 ch->flags &= ~flag; in sh_cmt_stop()
601 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { in sh_cmt_stop()
604 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_stop()
608 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) in sh_cmt_stop()
609 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_stop()
611 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_stop()
614 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_stop()
627 if (ch->cmt->num_channels == 1) { in sh_cmt_clocksource_read()
632 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_clocksource_read()
633 value = ch->total_cycles; in sh_cmt_clocksource_read()
637 raw += ch->match_value + 1; in sh_cmt_clocksource_read()
638 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_clocksource_read()
651 WARN_ON(ch->cs_enabled); in sh_cmt_clocksource_enable()
653 ch->total_cycles = 0; in sh_cmt_clocksource_enable()
657 ch->cs_enabled = true; in sh_cmt_clocksource_enable()
666 WARN_ON(!ch->cs_enabled); in sh_cmt_clocksource_disable()
669 ch->cs_enabled = false; in sh_cmt_clocksource_disable()
676 if (!ch->cs_enabled) in sh_cmt_clocksource_suspend()
680 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); in sh_cmt_clocksource_suspend()
687 if (!ch->cs_enabled) in sh_cmt_clocksource_resume()
690 dev_pm_genpd_resume(&ch->cmt->pdev->dev); in sh_cmt_clocksource_resume()
697 struct clocksource *cs = &ch->cs; in sh_cmt_register_clocksource()
699 cs->name = name; in sh_cmt_register_clocksource()
700 cs->rating = 125; in sh_cmt_register_clocksource()
701 cs->read = sh_cmt_clocksource_read; in sh_cmt_register_clocksource()
702 cs->enable = sh_cmt_clocksource_enable; in sh_cmt_register_clocksource()
703 cs->disable = sh_cmt_clocksource_disable; in sh_cmt_register_clocksource()
704 cs->suspend = sh_cmt_clocksource_suspend; in sh_cmt_register_clocksource()
705 cs->resume = sh_cmt_clocksource_resume; in sh_cmt_register_clocksource()
706 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); in sh_cmt_register_clocksource()
707 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; in sh_cmt_register_clocksource()
709 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", in sh_cmt_register_clocksource()
710 ch->index); in sh_cmt_register_clocksource()
712 clocksource_register_hz(cs, ch->cmt->rate); in sh_cmt_register_clocksource()
726 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); in sh_cmt_clock_event_start()
728 sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_clock_event_start()
748 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", in sh_cmt_clock_event_set_state()
749 ch->index, periodic ? "periodic" : "oneshot"); in sh_cmt_clock_event_set_state()
770 if (likely(ch->flags & FLAG_IRQCONTEXT)) in sh_cmt_clock_event_next()
771 ch->next_match_value = delta - 1; in sh_cmt_clock_event_next()
773 sh_cmt_set_next(ch, delta - 1); in sh_cmt_clock_event_next()
782 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); in sh_cmt_clock_event_suspend()
783 clk_unprepare(ch->cmt->clk); in sh_cmt_clock_event_suspend()
790 clk_prepare(ch->cmt->clk); in sh_cmt_clock_event_resume()
791 dev_pm_genpd_resume(&ch->cmt->pdev->dev); in sh_cmt_clock_event_resume()
797 struct clock_event_device *ced = &ch->ced; in sh_cmt_register_clockevent()
801 irq = platform_get_irq(ch->cmt->pdev, ch->index); in sh_cmt_register_clockevent()
807 dev_name(&ch->cmt->pdev->dev), ch); in sh_cmt_register_clockevent()
809 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", in sh_cmt_register_clockevent()
810 ch->index, irq); in sh_cmt_register_clockevent()
814 ced->name = name; in sh_cmt_register_clockevent()
815 ced->features = CLOCK_EVT_FEAT_PERIODIC; in sh_cmt_register_clockevent()
816 ced->features |= CLOCK_EVT_FEAT_ONESHOT; in sh_cmt_register_clockevent()
817 ced->rating = 125; in sh_cmt_register_clockevent()
818 ced->cpumask = cpu_possible_mask; in sh_cmt_register_clockevent()
819 ced->set_next_event = sh_cmt_clock_event_next; in sh_cmt_register_clockevent()
820 ced->set_state_shutdown = sh_cmt_clock_event_shutdown; in sh_cmt_register_clockevent()
821 ced->set_state_periodic = sh_cmt_clock_event_set_periodic; in sh_cmt_register_clockevent()
822 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; in sh_cmt_register_clockevent()
823 ced->suspend = sh_cmt_clock_event_suspend; in sh_cmt_register_clockevent()
824 ced->resume = sh_cmt_clock_event_resume; in sh_cmt_register_clockevent()
827 ced->shift = 32; in sh_cmt_register_clockevent()
828 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); in sh_cmt_register_clockevent()
829 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); in sh_cmt_register_clockevent()
830 ced->max_delta_ticks = ch->max_match_value; in sh_cmt_register_clockevent()
831 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); in sh_cmt_register_clockevent()
832 ced->min_delta_ticks = 0x1f; in sh_cmt_register_clockevent()
834 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", in sh_cmt_register_clockevent()
835 ch->index); in sh_cmt_register_clockevent()
847 ch->cmt->has_clockevent = true; in sh_cmt_register()
854 ch->cmt->has_clocksource = true; in sh_cmt_register()
872 ch->cmt = cmt; in sh_cmt_setup_channel()
873 ch->index = index; in sh_cmt_setup_channel()
874 ch->hwidx = hwidx; in sh_cmt_setup_channel()
875 ch->timer_bit = hwidx; in sh_cmt_setup_channel()
879 * timers with a per-channel start/stop register, compute its address in sh_cmt_setup_channel()
882 switch (cmt->info->model) { in sh_cmt_setup_channel()
884 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; in sh_cmt_setup_channel()
888 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; in sh_cmt_setup_channel()
892 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; in sh_cmt_setup_channel()
893 ch->ioctrl = ch->iostart + 0x10; in sh_cmt_setup_channel()
894 ch->timer_bit = 0; in sh_cmt_setup_channel()
897 value = ioread32(cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
899 iowrite32(value, cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
903 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) in sh_cmt_setup_channel()
904 ch->max_match_value = ~0; in sh_cmt_setup_channel()
906 ch->max_match_value = (1 << cmt->info->width) - 1; in sh_cmt_setup_channel()
908 ch->match_value = ch->max_match_value; in sh_cmt_setup_channel()
909 raw_spin_lock_init(&ch->lock); in sh_cmt_setup_channel()
911 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), in sh_cmt_setup_channel()
914 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", in sh_cmt_setup_channel()
915 ch->index); in sh_cmt_setup_channel()
918 ch->cs_enabled = false; in sh_cmt_setup_channel()
927 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); in sh_cmt_map_memory()
929 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); in sh_cmt_map_memory()
930 return -ENXIO; in sh_cmt_map_memory()
933 cmt->mapbase = ioremap(mem->start, resource_size(mem)); in sh_cmt_map_memory()
934 if (cmt->mapbase == NULL) { in sh_cmt_map_memory()
935 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); in sh_cmt_map_memory()
936 return -ENXIO; in sh_cmt_map_memory()
943 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
944 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
952 .compatible = "renesas,cmt-48",
957 .compatible = "renesas,cmt-48-gen2",
961 .compatible = "renesas,r8a7740-cmt1",
965 .compatible = "renesas,sh73a0-cmt1",
969 .compatible = "renesas,rcar-gen2-cmt0",
973 .compatible = "renesas,rcar-gen2-cmt1",
977 .compatible = "renesas,rcar-gen3-cmt0",
981 .compatible = "renesas,rcar-gen3-cmt1",
985 .compatible = "renesas,rcar-gen4-cmt0",
989 .compatible = "renesas,rcar-gen4-cmt1",
1002 cmt->pdev = pdev; in sh_cmt_setup()
1003 raw_spin_lock_init(&cmt->lock); in sh_cmt_setup()
1005 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { in sh_cmt_setup()
1006 cmt->info = of_device_get_match_data(&pdev->dev); in sh_cmt_setup()
1007 cmt->hw_channels = cmt->info->channels_mask; in sh_cmt_setup()
1008 } else if (pdev->dev.platform_data) { in sh_cmt_setup()
1009 struct sh_timer_config *cfg = pdev->dev.platform_data; in sh_cmt_setup()
1010 const struct platform_device_id *id = pdev->id_entry; in sh_cmt_setup()
1012 cmt->info = (const struct sh_cmt_info *)id->driver_data; in sh_cmt_setup()
1013 cmt->hw_channels = cfg->channels_mask; in sh_cmt_setup()
1015 dev_err(&cmt->pdev->dev, "missing platform data\n"); in sh_cmt_setup()
1016 return -ENXIO; in sh_cmt_setup()
1020 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); in sh_cmt_setup()
1021 if (IS_ERR(cmt->clk)) { in sh_cmt_setup()
1022 dev_err(&cmt->pdev->dev, "cannot get clock\n"); in sh_cmt_setup()
1023 return PTR_ERR(cmt->clk); in sh_cmt_setup()
1026 ret = clk_prepare(cmt->clk); in sh_cmt_setup()
1031 ret = clk_enable(cmt->clk); in sh_cmt_setup()
1035 if (cmt->info->width == 16) in sh_cmt_setup()
1036 cmt->rate = clk_get_rate(cmt->clk) / 512; in sh_cmt_setup()
1038 cmt->rate = clk_get_rate(cmt->clk) / 8; in sh_cmt_setup()
1046 cmt->num_channels = hweight8(cmt->hw_channels); in sh_cmt_setup()
1047 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), in sh_cmt_setup()
1049 if (cmt->channels == NULL) { in sh_cmt_setup()
1050 ret = -ENOMEM; in sh_cmt_setup()
1058 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { in sh_cmt_setup()
1059 unsigned int hwidx = ffs(mask) - 1; in sh_cmt_setup()
1060 bool clocksource = i == 1 || cmt->num_channels == 1; in sh_cmt_setup()
1063 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, in sh_cmt_setup()
1071 clk_disable(cmt->clk); in sh_cmt_setup()
1078 kfree(cmt->channels); in sh_cmt_setup()
1079 iounmap(cmt->mapbase); in sh_cmt_setup()
1081 clk_disable(cmt->clk); in sh_cmt_setup()
1083 clk_unprepare(cmt->clk); in sh_cmt_setup()
1085 clk_put(cmt->clk); in sh_cmt_setup()
1095 pm_runtime_set_active(&pdev->dev); in sh_cmt_probe()
1096 pm_runtime_enable(&pdev->dev); in sh_cmt_probe()
1100 dev_info(&pdev->dev, "kept as earlytimer\n"); in sh_cmt_probe()
1106 return -ENOMEM; in sh_cmt_probe()
1111 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()
1118 if (cmt->has_clockevent || cmt->has_clocksource) in sh_cmt_probe()
1119 pm_runtime_irq_safe(&pdev->dev); in sh_cmt_probe()
1121 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()
1128 return -EBUSY; /* cannot unregister clockevent and clocksource */ in sh_cmt_remove()