1 // SPDX-License-Identifier: GPL-2.0-only
48  * We are expecting to be clocked by the ARM peripheral clock.
61  * 1. Read the upper 32-bit timer counter register
62  * 2. Read the lower 32-bit timer counter register
63  * 3. Read the upper 32-bit timer counter register again. If the value is
64  *  different to the 32-bit upper value read previously, go back to step 2.
65  *  Otherwise the 64-bit timer counter value is correct.
95  * 2. Write the lower 32-bit Comparator Value Register.
96  * 3. Write the upper 32-bit Comparator Value Register.
156 	 * the same event in single-shot mode)  in gt_clockevent_interrupt()
158 	 *	Either disable single-shot mode.  in gt_clockevent_interrupt()
169 	evt->event_handler(evt);  in gt_clockevent_interrupt()
178 	clk->name = "arm_global_timer";  in gt_starting_cpu()
179 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |  in gt_starting_cpu()
181 	clk->set_state_shutdown = gt_clockevent_shutdown;  in gt_starting_cpu()
182 	clk->set_state_periodic = gt_clockevent_set_periodic;  in gt_starting_cpu()
183 	clk->set_state_oneshot = gt_clockevent_shutdown;  in gt_starting_cpu()
184 	clk->set_state_oneshot_stopped = gt_clockevent_shutdown;  in gt_starting_cpu()
185 	clk->set_next_event = gt_clockevent_set_next_event;  in gt_starting_cpu()
186 	clk->cpumask = cpumask_of(cpu);  in gt_starting_cpu()
187 	clk->rating = 300;  in gt_starting_cpu()
188 	clk->irq = gt_ppi;  in gt_starting_cpu()
191 	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);  in gt_starting_cpu()
200 	disable_percpu_irq(clk->irq);  in gt_dying_cpu()
215 		/* re-enable timer on resume */  in gt_resume()
275 	writel(((CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) <<  in gt_clocksource_init()
295 		psv = DIV_ROUND_CLOSEST(ndata->new_rate,  in gt_clk_rate_change_cb()
298 		if (abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)  in gt_clk_rate_change_cb()
301 		psv--;  in gt_clk_rate_change_cb()
313 		/* scale down: adjust divider in post-change notification */  in gt_clk_rate_change_cb()
314 		if (ndata->new_rate < ndata->old_rate)  in gt_clk_rate_change_cb()
317 		/* scale up: adjust divider now - before frequency change */  in gt_clk_rate_change_cb()
322 		/* scale up: pre-change notification did the adjustment */  in gt_clk_rate_change_cb()
323 		if (ndata->new_rate > ndata->old_rate)  in gt_clk_rate_change_cb()
326 		/* scale down: adjust divider now - after frequency change */  in gt_clk_rate_change_cb()
332 		if (ndata->new_rate < ndata->old_rate)  in gt_clk_rate_change_cb()
358 		pr_warn("global-timer: non support for this cpu version.\n");  in global_timer_of_register()
359 		return -ENOSYS;  in global_timer_of_register()
364 		pr_warn("global-timer: unable to parse irq\n");  in global_timer_of_register()
365 		return -EINVAL;  in global_timer_of_register()
370 		pr_warn("global-timer: invalid base address\n");  in global_timer_of_register()
371 		return -ENXIO;  in global_timer_of_register()
380 		pr_warn("global-timer: clk not found\n");  in global_timer_of_register()
381 		err = -EINVAL;  in global_timer_of_register()
397 		pr_warn("global-timer: can't allocate memory\n");  in global_timer_of_register()
398 		err = -ENOMEM;  in global_timer_of_register()
405 		pr_warn("global-timer: can't register interrupt %d (%d)\n",  in global_timer_of_register()
441 TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",