Lines Matching +full:multi +full:- +full:system
1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
201 Support for Multi Timer Unit. MTU provides access
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
294 bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
298 This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP).
316 power-of-2 divisor of the clock rate. The behaviour can also be
319 The main use of the event stream is wfe-based timeouts of userspace
330 bool "Workaround for Freescale/NXP Erratum A-008585"
336 A-008585 ("ARM generic timer may contain an erroneous
338 fsl,erratum-a008585 property is found in the timer node.
347 161010101. The workaround will be active if the hisilicon,erratum-161010101
351 bool "Workaround for Cortex-A73 erratum 858921"
356 This option enables a workaround applicable to Cortex-A73
369 allwinner,erratum-unknown1 property is found in the timer node.
406 bool "Support for the ARMv7M system time" if COMPILE_TEST
410 This option enables support for the ARMv7M system timer unit.
435 bool "Exynos multi core timer driver" if COMPILE_TEST
439 Support for Multi Core Timer controller on Exynos SoCs.
501 bool "J-Core PIT timer driver" if COMPILE_TEST
507 the integrated PIT in the J-Core synthesizable, open source SoC.
515 the Compare Match Timer (CMT) hardware available in 16/32/48-bit
523 This enables build of a clockevent driver for the Multi-Function
525 This hardware comes with 16-bit timer registers.
541 the 32-bit Timer Unit (TMU) hardware available on a wide range
550 the 48-bit System Timer (STI) hardware available on a SoCs
568 counter available in the "System Registers" block of
578 bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
582 This enables OST0 support available on PXA and SA-11x0
600 bool "i.MX system counter timer" if COMPILE_TEST
603 Enable this option to use i.MX system counter timer as a
624 bool "Timer for the RISC-V platform" if COMPILE_TEST
629 This enables the per-hart timer built into all RISC-V systems, which
631 required for all RISC-V systems.
634 bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
639 This option enables the CLINT timer for RISC-V systems. The CLINT
640 driver is usually used for NoMMU RISC-V systems.
643 bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
647 Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP
648 system.
649 csky,mptimer is not only used in SMP system, it also could be used in
650 single core system. It's not a mmio reg and it uses mtcr/mfcr instruction.
653 bool "Gx6605s SOC system timer driver" if COMPILE_TEST
676 programmable 32-bit free running incrementing counters.
705 Support for the Operating System Timer of the Ingenic JZ SoCs.
713 based system. It supports the oneshot, the periodic
718 bool "Clocksource using goldfish-rtc"
722 Support for the timer/counter of goldfish-rtc