3  * Zynq UltraScale+ MPSoC Divider support
7  * Adjustable divider clock implementation
16  * DOC: basic adjustable divider clock that cannot gate
32  * struct zynqmp_clk_divider - adjustable divider clock
35  * @is_frac:	The divider is a fractional divider
73  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
82 	struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);  in zynqmp_clk_divider_recalc_rate()  local
84 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_recalc_rate()
85 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_recalc_rate()
92 		pr_debug("%s() get divider failed for %s, ret = %d\n",  in zynqmp_clk_divider_recalc_rate()
100 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_recalc_rate()
104 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in zynqmp_clk_divider_recalc_rate()
115 				    struct zynqmp_clk_divider *divider,  in zynqmp_get_divider2_val()  argument
140 		for (div2 = 1; div2 <= divider->max_div;) {  in zynqmp_get_divider2_val()
147 			if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_get_divider2_val()
160  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
171 	struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);  in zynqmp_clk_divider_round_rate()  local
173 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_round_rate()
174 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_round_rate()
179 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in zynqmp_clk_divider_round_rate()
183 			pr_debug("%s() get divider failed for %s, ret = %d\n",  in zynqmp_clk_divider_round_rate()
190 		if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_round_rate()
196 	bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);  in zynqmp_clk_divider_round_rate()
199 	 * In case of two divisors, compute best divider values and return  in zynqmp_clk_divider_round_rate()
201 	 * set to optimum based on required total divider value.  in zynqmp_clk_divider_round_rate()
205 		zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);  in zynqmp_clk_divider_round_rate()
208 	if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)  in zynqmp_clk_divider_round_rate()
211 	bestdiv = min_t(u32, bestdiv, divider->max_div);  in zynqmp_clk_divider_round_rate()
218  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
228 	struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);  in zynqmp_clk_divider_set_rate()  local
230 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_set_rate()
231 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_set_rate()
235 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
244 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_set_rate()
250 		pr_debug("%s() set divider failed for %s, ret = %d\n",  in zynqmp_clk_divider_set_rate()
270  * @type:		Divider type
319  * zynqmp_clk_register_divider() - Register a divider clock
326  * Return: clock hardware to registered clock divider
339 	/* allocate the divider */  in zynqmp_clk_register_divider()
364 	 * To achieve best possible rate, maximum limit of divider is required  in zynqmp_clk_register_divider()