55 /* Extract divider instance from clock hardware instance */
91  * struct clk_wzrd_divider - clock divider specific to clk_wzrd
94  * @base:	base address of register containing the divider
95  * @offset:	offset address of register containing the divider
96  * @shift:	shift to the divider bit field
97  * @width:	width of the divider bit field
98  * @flags:	clk_wzrd divider flags
99  * @table:	array of value/divider pairs, last entry should have div = 0
110 	spinlock_t *lock;  /* divider lock */
128 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate()  local
129 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate()
132 	val = readl(div_addr) >> divider->shift;  in clk_wzrd_recalc_rate()
133 	val &= div_mask(divider->width);  in clk_wzrd_recalc_rate()
135 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_wzrd_recalc_rate()
136 			divider->flags, divider->width);  in clk_wzrd_recalc_rate()
145 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig()  local
146 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig()
148 	if (divider->lock)  in clk_wzrd_dynamic_reconfig()
149 		spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
151 		__acquire(divider->lock);  in clk_wzrd_dynamic_reconfig()
163 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
171 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
173 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
176 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
180 	if (divider->lock)  in clk_wzrd_dynamic_reconfig()
181 		spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
183 		__release(divider->lock);  in clk_wzrd_dynamic_reconfig()
212 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_ratef()  local
213 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_ratef()
216 	div = val & div_mask(divider->width);  in clk_wzrd_recalc_ratef()
228 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig_f()  local
229 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig_f()
246 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
254 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
256 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
259 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
517 		dev_err(&pdev->dev, "unable to register divider clock\n");  in clk_wzrd_probe()
556 				"unable to register divider clock\n");  in clk_wzrd_probe()