Lines Matching +full:reg +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "clk-cgu.h"
13 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
14 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
15 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) { in lgm_clk_register_fixed()
30 spin_lock_irqsave(&ctx->lock, flags); in lgm_clk_register_fixed()
31 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
32 list->div_width, list->div_val); in lgm_clk_register_fixed()
33 spin_unlock_irqrestore(&ctx->lock, flags); in lgm_clk_register_fixed()
36 return clk_hw_register_fixed_rate(NULL, list->name, in lgm_clk_register_fixed()
37 list->parent_data[0].name, in lgm_clk_register_fixed()
38 list->flags, list->mux_flags); in lgm_clk_register_fixed()
43 struct lgm_clk_mux *mux = to_lgm_clk_mux(hw); in lgm_clk_mux_get_parent() local
47 spin_lock_irqsave(&mux->lock, flags); in lgm_clk_mux_get_parent()
48 if (mux->flags & MUX_CLK_SW) in lgm_clk_mux_get_parent()
49 val = mux->reg; in lgm_clk_mux_get_parent()
51 val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_get_parent()
52 mux->width); in lgm_clk_mux_get_parent()
53 spin_unlock_irqrestore(&mux->lock, flags); in lgm_clk_mux_get_parent()
54 return clk_mux_val_to_index(hw, NULL, mux->flags, val); in lgm_clk_mux_get_parent()
59 struct lgm_clk_mux *mux = to_lgm_clk_mux(hw); in lgm_clk_mux_set_parent() local
63 val = clk_mux_index_to_val(NULL, mux->flags, index); in lgm_clk_mux_set_parent()
64 spin_lock_irqsave(&mux->lock, flags); in lgm_clk_mux_set_parent()
65 if (mux->flags & MUX_CLK_SW) in lgm_clk_mux_set_parent()
66 mux->reg = val; in lgm_clk_mux_set_parent()
68 lgm_set_clk_val(mux->membase, mux->reg, mux->shift, in lgm_clk_mux_set_parent()
69 mux->width, val); in lgm_clk_mux_set_parent()
70 spin_unlock_irqrestore(&mux->lock, flags); in lgm_clk_mux_set_parent()
78 struct lgm_clk_mux *mux = to_lgm_clk_mux(hw); in lgm_clk_mux_determine_rate() local
80 return clk_mux_determine_rate_flags(hw, req, mux->flags); in lgm_clk_mux_determine_rate()
93 unsigned long flags, cflags = list->mux_flags; in lgm_clk_register_mux()
94 struct device *dev = ctx->dev; in lgm_clk_register_mux()
95 u8 shift = list->mux_shift; in lgm_clk_register_mux()
96 u8 width = list->mux_width; in lgm_clk_register_mux()
98 struct lgm_clk_mux *mux; in lgm_clk_register_mux() local
99 u32 reg = list->mux_off; in lgm_clk_register_mux() local
103 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); in lgm_clk_register_mux()
104 if (!mux) in lgm_clk_register_mux()
105 return ERR_PTR(-ENOMEM); in lgm_clk_register_mux()
107 init.name = list->name; in lgm_clk_register_mux()
109 init.flags = list->flags; in lgm_clk_register_mux()
110 init.parent_data = list->parent_data; in lgm_clk_register_mux()
111 init.num_parents = list->num_parents; in lgm_clk_register_mux()
113 mux->membase = ctx->membase; in lgm_clk_register_mux()
114 mux->lock = ctx->lock; in lgm_clk_register_mux()
115 mux->reg = reg; in lgm_clk_register_mux()
116 mux->shift = shift; in lgm_clk_register_mux()
117 mux->width = width; in lgm_clk_register_mux()
118 mux->flags = cflags; in lgm_clk_register_mux()
119 mux->hw.init = &init; in lgm_clk_register_mux()
121 hw = &mux->hw; in lgm_clk_register_mux()
127 spin_lock_irqsave(&mux->lock, flags); in lgm_clk_register_mux()
128 lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); in lgm_clk_register_mux()
129 spin_unlock_irqrestore(&mux->lock, flags); in lgm_clk_register_mux()
142 spin_lock_irqsave(÷r->lock, flags); in lgm_clk_divider_recalc_rate()
143 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
144 divider->shift, divider->width); in lgm_clk_divider_recalc_rate()
145 spin_unlock_irqrestore(÷r->lock, flags); in lgm_clk_divider_recalc_rate()
147 return divider_recalc_rate(hw, parent_rate, val, divider->table, in lgm_clk_divider_recalc_rate()
148 divider->flags, divider->width); in lgm_clk_divider_recalc_rate()
157 return divider_round_rate(hw, rate, prate, divider->table, in lgm_clk_divider_round_rate()
158 divider->width, divider->flags); in lgm_clk_divider_round_rate()
169 value = divider_get_val(rate, prate, divider->table, in lgm_clk_divider_set_rate()
170 divider->width, divider->flags); in lgm_clk_divider_set_rate()
174 spin_lock_irqsave(÷r->lock, flags); in lgm_clk_divider_set_rate()
175 lgm_set_clk_val(divider->membase, divider->reg, in lgm_clk_divider_set_rate()
176 divider->shift, divider->width, value); in lgm_clk_divider_set_rate()
177 spin_unlock_irqrestore(÷r->lock, flags); in lgm_clk_divider_set_rate()
187 spin_lock_irqsave(&div->lock, flags); in lgm_clk_divider_enable_disable()
188 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
189 div->width_gate, enable); in lgm_clk_divider_enable_disable()
190 spin_unlock_irqrestore(&div->lock, flags); in lgm_clk_divider_enable_disable()
216 unsigned long flags, cflags = list->div_flags; in lgm_clk_register_divider()
217 struct device *dev = ctx->dev; in lgm_clk_register_divider()
220 u8 shift = list->div_shift; in lgm_clk_register_divider()
221 u8 width = list->div_width; in lgm_clk_register_divider()
222 u8 shift_gate = list->div_shift_gate; in lgm_clk_register_divider()
223 u8 width_gate = list->div_width_gate; in lgm_clk_register_divider()
224 u32 reg = list->div_off; in lgm_clk_register_divider() local
230 return ERR_PTR(-ENOMEM); in lgm_clk_register_divider()
232 init.name = list->name; in lgm_clk_register_divider()
234 init.flags = list->flags; in lgm_clk_register_divider()
235 init.parent_data = list->parent_data; in lgm_clk_register_divider()
238 div->membase = ctx->membase; in lgm_clk_register_divider()
239 div->lock = ctx->lock; in lgm_clk_register_divider()
240 div->reg = reg; in lgm_clk_register_divider()
241 div->shift = shift; in lgm_clk_register_divider()
242 div->width = width; in lgm_clk_register_divider()
243 div->shift_gate = shift_gate; in lgm_clk_register_divider()
244 div->width_gate = width_gate; in lgm_clk_register_divider()
245 div->flags = cflags; in lgm_clk_register_divider()
246 div->table = list->div_table; in lgm_clk_register_divider()
247 div->hw.init = &init; in lgm_clk_register_divider()
249 hw = &div->hw; in lgm_clk_register_divider()
255 spin_lock_irqsave(&div->lock, flags); in lgm_clk_register_divider()
256 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); in lgm_clk_register_divider()
257 spin_unlock_irqrestore(&div->lock, flags); in lgm_clk_register_divider()
270 hw = clk_hw_register_fixed_factor(ctx->dev, list->name, in lgm_clk_register_fixed_factor()
271 list->parent_data[0].name, list->flags, in lgm_clk_register_fixed_factor()
272 list->mult, list->div); in lgm_clk_register_fixed_factor()
276 if (list->div_flags & CLOCK_FLAG_VAL_INIT) { in lgm_clk_register_fixed_factor()
277 spin_lock_irqsave(&ctx->lock, flags); in lgm_clk_register_fixed_factor()
278 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed_factor()
279 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
280 spin_unlock_irqrestore(&ctx->lock, flags); in lgm_clk_register_fixed_factor()
290 unsigned int reg; in lgm_clk_gate_enable() local
292 spin_lock_irqsave(&gate->lock, flags); in lgm_clk_gate_enable()
293 reg = GATE_HW_REG_EN(gate->reg); in lgm_clk_gate_enable()
294 lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); in lgm_clk_gate_enable()
295 spin_unlock_irqrestore(&gate->lock, flags); in lgm_clk_gate_enable()
304 unsigned int reg; in lgm_clk_gate_disable() local
306 spin_lock_irqsave(&gate->lock, flags); in lgm_clk_gate_disable()
307 reg = GATE_HW_REG_DIS(gate->reg); in lgm_clk_gate_disable()
308 lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); in lgm_clk_gate_disable()
309 spin_unlock_irqrestore(&gate->lock, flags); in lgm_clk_gate_disable()
315 unsigned int reg, ret; in lgm_clk_gate_is_enabled() local
318 spin_lock_irqsave(&gate->lock, flags); in lgm_clk_gate_is_enabled()
319 reg = GATE_HW_REG_STAT(gate->reg); in lgm_clk_gate_is_enabled()
320 ret = lgm_get_clk_val(gate->membase, reg, gate->shift, 1); in lgm_clk_gate_is_enabled()
321 spin_unlock_irqrestore(&gate->lock, flags); in lgm_clk_gate_is_enabled()
336 unsigned long flags, cflags = list->gate_flags; in lgm_clk_register_gate()
337 const char *pname = list->parent_data[0].name; in lgm_clk_register_gate()
338 struct device *dev = ctx->dev; in lgm_clk_register_gate()
339 u8 shift = list->gate_shift; in lgm_clk_register_gate()
342 u32 reg = list->gate_off; in lgm_clk_register_gate() local
348 return ERR_PTR(-ENOMEM); in lgm_clk_register_gate()
350 init.name = list->name; in lgm_clk_register_gate()
352 init.flags = list->flags; in lgm_clk_register_gate()
356 gate->membase = ctx->membase; in lgm_clk_register_gate()
357 gate->lock = ctx->lock; in lgm_clk_register_gate()
358 gate->reg = reg; in lgm_clk_register_gate()
359 gate->shift = shift; in lgm_clk_register_gate()
360 gate->flags = cflags; in lgm_clk_register_gate()
361 gate->hw.init = &init; in lgm_clk_register_gate()
363 hw = &gate->hw; in lgm_clk_register_gate()
369 spin_lock_irqsave(&gate->lock, flags); in lgm_clk_register_gate()
370 lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val); in lgm_clk_register_gate()
371 spin_unlock_irqrestore(&gate->lock, flags); in lgm_clk_register_gate()
385 switch (list->type) { in lgm_clk_register_branches()
402 dev_err(ctx->dev, "invalid clk type\n"); in lgm_clk_register_branches()
403 return -EINVAL; in lgm_clk_register_branches()
407 dev_err(ctx->dev, in lgm_clk_register_branches()
409 list->name, list->type); in lgm_clk_register_branches()
410 return -EIO; in lgm_clk_register_branches()
412 ctx->clk_data.hws[list->id] = hw; in lgm_clk_register_branches()
425 div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
426 ddiv->shift0, ddiv->width0) + 1; in lgm_clk_ddiv_recalc_rate()
427 div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
428 ddiv->shift1, ddiv->width1) + 1; in lgm_clk_ddiv_recalc_rate()
429 exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
430 ddiv->shift2, ddiv->width2); in lgm_clk_ddiv_recalc_rate()
436 do_div(prate, ddiv->div); in lgm_clk_ddiv_recalc_rate()
437 prate *= ddiv->mult; in lgm_clk_ddiv_recalc_rate()
448 spin_lock_irqsave(&ddiv->lock, flags); in lgm_clk_ddiv_enable()
449 lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate, in lgm_clk_ddiv_enable()
450 ddiv->width_gate, 1); in lgm_clk_ddiv_enable()
451 spin_unlock_irqrestore(&ddiv->lock, flags); in lgm_clk_ddiv_enable()
460 spin_lock_irqsave(&ddiv->lock, flags); in lgm_clk_ddiv_disable()
461 lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate, in lgm_clk_ddiv_disable()
462 ddiv->width_gate, 0); in lgm_clk_ddiv_disable()
463 spin_unlock_irqrestore(&ddiv->lock, flags); in lgm_clk_ddiv_disable()
485 return -EINVAL; in lgm_clk_get_ddiv_val()
504 spin_lock_irqsave(&ddiv->lock, flags); in lgm_clk_ddiv_set_rate()
505 if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { in lgm_clk_ddiv_set_rate()
511 spin_unlock_irqrestore(&ddiv->lock, flags); in lgm_clk_ddiv_set_rate()
512 return -EINVAL; in lgm_clk_ddiv_set_rate()
516 spin_unlock_irqrestore(&ddiv->lock, flags); in lgm_clk_ddiv_set_rate()
517 return -EINVAL; in lgm_clk_ddiv_set_rate()
520 lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift0, ddiv->width0, in lgm_clk_ddiv_set_rate()
521 ddiv1 - 1); in lgm_clk_ddiv_set_rate()
523 lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift1, ddiv->width1, in lgm_clk_ddiv_set_rate()
524 ddiv2 - 1); in lgm_clk_ddiv_set_rate()
525 spin_unlock_irqrestore(&ddiv->lock, flags); in lgm_clk_ddiv_set_rate()
542 spin_lock_irqsave(&ddiv->lock, flags); in lgm_clk_ddiv_round_rate()
543 if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { in lgm_clk_ddiv_round_rate()
547 spin_unlock_irqrestore(&ddiv->lock, flags); in lgm_clk_ddiv_round_rate()
554 return -EINVAL; in lgm_clk_ddiv_round_rate()
561 spin_lock_irqsave(&ddiv->lock, flags); in lgm_clk_ddiv_round_rate()
562 if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { in lgm_clk_ddiv_round_rate()
566 spin_unlock_irqrestore(&ddiv->lock, flags); in lgm_clk_ddiv_round_rate()
583 struct device *dev = ctx->dev; in lgm_clk_register_ddiv()
594 return -ENOMEM; in lgm_clk_register_ddiv()
596 init.name = list->name; in lgm_clk_register_ddiv()
598 init.flags = list->flags; in lgm_clk_register_ddiv()
599 init.parent_data = list->parent_data; in lgm_clk_register_ddiv()
602 ddiv->membase = ctx->membase; in lgm_clk_register_ddiv()
603 ddiv->lock = ctx->lock; in lgm_clk_register_ddiv()
604 ddiv->reg = list->reg; in lgm_clk_register_ddiv()
605 ddiv->shift0 = list->shift0; in lgm_clk_register_ddiv()
606 ddiv->width0 = list->width0; in lgm_clk_register_ddiv()
607 ddiv->shift1 = list->shift1; in lgm_clk_register_ddiv()
608 ddiv->width1 = list->width1; in lgm_clk_register_ddiv()
609 ddiv->shift_gate = list->shift_gate; in lgm_clk_register_ddiv()
610 ddiv->width_gate = list->width_gate; in lgm_clk_register_ddiv()
611 ddiv->shift2 = list->ex_shift; in lgm_clk_register_ddiv()
612 ddiv->width2 = list->ex_width; in lgm_clk_register_ddiv()
613 ddiv->flags = list->div_flags; in lgm_clk_register_ddiv()
614 ddiv->mult = 2; in lgm_clk_register_ddiv()
615 ddiv->div = 5; in lgm_clk_register_ddiv()
616 ddiv->hw.init = &init; in lgm_clk_register_ddiv()
618 hw = &ddiv->hw; in lgm_clk_register_ddiv()
621 dev_err(dev, "register clk: %s failed!\n", list->name); in lgm_clk_register_ddiv()
624 ctx->clk_data.hws[list->id] = hw; in lgm_clk_register_ddiv()