Lines Matching +full:enable +full:- +full:frequency +full:- +full:shift
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
120 u8 shift; member
136 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
146 * (1) Input frequency range (REF).
147 * (2) Comparison frequency range (CF). CF = REF/DIVM.
148 * (3) VCO frequency range (VCO). VCO = CF * DIVN.
150 * The final PLL output frequency (FO) = VCO >> DIVP.
154 * struct tegra_clk_pll_freq_table - PLL frequecy table
175 * struct pdiv_map - map post divider to hw value
186 * struct div_nmp - offset and width of m,n and p fields
188 * @divn_shift: shift to the feedback divider bit field
190 * @divm_shift: shift to the input divider bit field
192 * @divp_shift: shift to the post divider bit field
194 * @override_divn_shift: shift to the feedback divider bitfield in override reg
195 * @override_divm_shift: shift to the input divider bitfield in override reg
196 * @override_divp_shift: shift to the post divider bitfield in override reg
215 * struct tegra_clk_pll_params - PLL parameters
217 * @input_min: Minimum input frequency
218 * @input_max: Maximum input frequency
219 * @cf_min: Minimum comparison frequency
220 * @cf_max: Maximum comparison frequency
221 * @vco_min: Minimum VCO frequency
222 * @vco_max: Maximum VCO frequency
227 * @lock_enable_bit_idx: Bit index to enable PLL lock
229 * @iddq_bit_idx: Bit index to enable PLL IDDQ
231 * @reset_bit_idx: Shift of reset bit in reset_reg
234 * @sdm_ctrl_reg: Register offset where SDM enable is
235 * @sdm_ctrl_en_mask: Mask of SDM enable bit
237 * @ssc_ctrl_en_mask: Mask of SSC enable bit
244 * @stepa_shift: Dynamic ramp step A field shift
245 * @stepb_shift: Dynamic ramp step B field shift
275 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
277 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
278 * to be programmed to change output frequency of the PLL.
279 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
280 * to be programmed to change output frequency of the PLL.
281 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
282 * to be programmed to change output frequency of the PLL.
283 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
285 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
287 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
289 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
290 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
292 * TEGRA_PLL_BYPASS - PLL has bypass bit
293 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
294 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
296 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
298 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
369 * struct tegra_clk_pll - Tegra PLL clock
371 * @hw: handle between common and hardware-specifix interfaces
388 * struct tegra_audio_clk_info - Tegra Audio Clk Information
497 * struct tegra_clk_pll_out - PLL divider down clock
499 * @hw: handle between common and hardware-specific interfaces
501 * @enb_bit_idx: bit to enable/disable PLL divider
504 * @flags: hardware-specific flags
524 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
526 * @enb_reg: read the enable status
527 * @enb_set_reg: write 1 to enable clock
543 * struct tegra_clk_periph_gate - peripheral gate clock
546 * @hw: handle between common and hardware-specific interfaces
549 * @flags: hardware-specific flags
554 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
556 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
559 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
605 * struct clk-periph - peripheral clock
608 * @hw: handle between common and hardware-specific interfaces
649 .shift = _mux_shift, \
656 .shift = _div_shift, \
711 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
720 * struct clk_super_mux - super clock
722 * @hw: handle between common and hardware-specific interfaces
725 * @flags: hardware-specific flags
726 * @div2_index: bit controlling divide-by-2
731 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
733 * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
736 * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
737 * clocks, it only has a clock-skipper.
774 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
776 * @hw: handle between common and hardware-specific interfaces
778 * @flags: hardware-specific flags
799 * struct clk_init_table - clock initialization table
803 * @state: enable/disable
813 * struct clk_duplicate - duplicate clocks
912 void tegra_clk_set_pllp_out_cpu(bool enable);