Lines Matching +full:tegra20 +full:- +full:dsi
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/tegra20-car.h>
19 #include "clk-id.h"
445 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
446 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
447 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
449 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
451 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
452 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
453 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
455 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
456 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
457 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
458 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
468 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
469 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
470 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
471 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
493 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
494 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
495 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
496 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
497 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
503 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
504 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
505 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
506 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
507 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
805 /* dsi */ in tegra20_periph_clk_init()
806 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, in tegra20_periph_clk_init()
808 clk_register_clkdev(clk, NULL, "dsi"); in tegra20_periph_clk_init()
841 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
846 clk = tegra_clk_register_periph_nodiv(data->name, in tegra20_periph_clk_init()
847 data->p.parent_names, in tegra20_periph_clk_init()
848 data->num_parents, &data->periph, in tegra20_periph_clk_init()
849 clk_base, data->offset); in tegra20_periph_clk_init()
850 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
876 /* Tegra20 CPU clock and reset control functions */
1058 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1059 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1060 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1067 { .compatible = "nvidia,tegra20-pmc" },
1084 if (clkspec->args[0] != TEGRA20_CLK_RTC && in tegra20_clk_src_onecell_get()
1085 clkspec->args[0] != TEGRA20_CLK_TWD && in tegra20_clk_src_onecell_get()
1086 clkspec->args[0] != TEGRA20_CLK_TIMER && in tegra20_clk_src_onecell_get()
1088 return ERR_PTR(-EPROBE_DEFER); in tegra20_clk_src_onecell_get()
1097 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent in tegra20_clk_src_onecell_get()
1103 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || in tegra20_clk_src_onecell_get()
1104 clkspec->args[0] == TEGRA20_CLK_CDEV2) { in tegra20_clk_src_onecell_get()
1107 return ERR_PTR(-EPROBE_DEFER); in tegra20_clk_src_onecell_get()
1110 if (clkspec->args[0] == TEGRA20_CLK_EMC) { in tegra20_clk_src_onecell_get()
1112 return ERR_PTR(-EPROBE_DEFER); in tegra20_clk_src_onecell_get()
1160 CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
1189 { .compatible = "nvidia,tegra20-car" },
1195 .name = "tegra20-car",