Lines Matching +full:pex +full:- +full:clk +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
16 #include <dt-bindings/clock/tegra20-car.h>
18 #include "clk.h"
19 #include "clk-id.h"
27 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
34 #define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
87 #define CCLK_RUN_POLICY 2
139 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
146 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
158 static struct clk **clks;
181 { 12000000, 216000000, 432, 12, 2, 8 },
182 { 13000000, 216000000, 432, 13, 2, 8 },
183 { 19200000, 216000000, 90, 4, 2, 1 },
184 { 26000000, 216000000, 432, 26, 2, 8 },
362 { .pdiv = 2, .hw_val = 0 },
445 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
446 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
447 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
449 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
451 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
452 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
453 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
455 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
456 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
457 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
461 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
468 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
469 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
470 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
471 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
474 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
492 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
493 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
494 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
495 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
496 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
497 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
503 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
504 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
505 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
506 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
507 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
510 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
616 return 2; in tegra20_get_pll_ref_div()
628 struct clk *clk; in tegra20_pll_init() local
631 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
633 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
636 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra20_pll_init()
639 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", in tegra20_pll_init()
642 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
645 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
647 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
650 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra20_pll_init()
653 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", in tegra20_pll_init()
656 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; in tegra20_pll_init()
659 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
661 clks[TEGRA20_CLK_PLL_X] = clk; in tegra20_pll_init()
664 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
666 clks[TEGRA20_CLK_PLL_U] = clk; in tegra20_pll_init()
669 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
671 clks[TEGRA20_CLK_PLL_D] = clk; in tegra20_pll_init()
674 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", in tegra20_pll_init()
675 CLK_SET_RATE_PARENT, 1, 2); in tegra20_pll_init()
676 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; in tegra20_pll_init()
679 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, in tegra20_pll_init()
681 clks[TEGRA20_CLK_PLL_A] = clk; in tegra20_pll_init()
684 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra20_pll_init()
687 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", in tegra20_pll_init()
690 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
693 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
695 clks[TEGRA20_CLK_PLL_E] = clk; in tegra20_pll_init()
707 struct clk *clk; in tegra20_super_clk_init() local
710 clk = tegra_clk_register_super_cclk("cclk", cclk_parents, in tegra20_super_clk_init()
714 clks[TEGRA20_CLK_CCLK] = clk; in tegra20_super_clk_init()
717 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); in tegra20_super_clk_init()
718 clks[TEGRA20_CLK_TWD] = clk; in tegra20_super_clk_init()
727 struct clk *clk; in tegra20_audio_clk_init() local
730 clk = clk_register_mux(NULL, "audio_mux", audio_parents, in tegra20_audio_clk_init()
734 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, in tegra20_audio_clk_init()
737 clks[TEGRA20_CLK_AUDIO] = clk; in tegra20_audio_clk_init()
740 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", in tegra20_audio_clk_init()
741 CLK_SET_RATE_PARENT, 2, 1); in tegra20_audio_clk_init()
742 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", in tegra20_audio_clk_init()
746 clks[TEGRA20_CLK_AUDIO_2X] = clk; in tegra20_audio_clk_init()
775 …TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB,…
776 …TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB,…
777 …TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB,…
778 …TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB,…
779 …TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB,…
780 …TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1…
781 …TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2…
787 struct clk *clk; in tegra20_periph_clk_init() local
791 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", in tegra20_periph_clk_init()
794 clks[TEGRA20_CLK_AC97] = clk; in tegra20_periph_clk_init()
797 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false); in tegra20_periph_clk_init()
799 clks[TEGRA20_CLK_EMC] = clk; in tegra20_periph_clk_init()
801 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra20_periph_clk_init()
803 clks[TEGRA20_CLK_MC] = clk; in tegra20_periph_clk_init()
806 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, in tegra20_periph_clk_init()
808 clk_register_clkdev(clk, NULL, "dsi"); in tegra20_periph_clk_init()
809 clks[TEGRA20_CLK_DSI] = clk; in tegra20_periph_clk_init()
811 /* pex */ in tegra20_periph_clk_init()
812 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, in tegra20_periph_clk_init()
814 clks[TEGRA20_CLK_PEX] = clk; in tegra20_periph_clk_init()
818 0, clk_base + MISC_CLK_ENB, 22, 2, in tegra20_periph_clk_init()
824 0, clk_base + MISC_CLK_ENB, 20, 2, in tegra20_periph_clk_init()
829 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, in tegra20_periph_clk_init()
831 clks[TEGRA20_CLK_CDEV1] = clk; in tegra20_periph_clk_init()
834 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, in tegra20_periph_clk_init()
836 clks[TEGRA20_CLK_CDEV2] = clk; in tegra20_periph_clk_init()
840 clk = tegra_clk_register_periph_data(clk_base, data); in tegra20_periph_clk_init()
841 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
846 clk = tegra_clk_register_periph_nodiv(data->name, in tegra20_periph_clk_init()
847 data->p.parent_names, in tegra20_periph_clk_init()
848 data->num_parents, &data->periph, in tegra20_periph_clk_init()
849 clk_base, data->offset); in tegra20_periph_clk_init()
850 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
858 struct clk *clk; in tegra20_osc_clk_init() local
865 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED, in tegra20_osc_clk_init()
867 clks[TEGRA20_CLK_CLK_M] = clk; in tegra20_osc_clk_init()
871 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", in tegra20_osc_clk_init()
873 clks[TEGRA20_CLK_PLL_REF] = clk; in tegra20_osc_clk_init()
1058 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1059 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1060 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1067 { .compatible = "nvidia,tegra20-pmc" },
1073 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, in tegra20_clk_src_onecell_get()
1078 struct clk *clk; in tegra20_clk_src_onecell_get() local
1084 if (clkspec->args[0] != TEGRA20_CLK_RTC && in tegra20_clk_src_onecell_get()
1085 clkspec->args[0] != TEGRA20_CLK_TWD && in tegra20_clk_src_onecell_get()
1086 clkspec->args[0] != TEGRA20_CLK_TIMER && in tegra20_clk_src_onecell_get()
1088 return ERR_PTR(-EPROBE_DEFER); in tegra20_clk_src_onecell_get()
1090 clk = of_clk_src_onecell_get(clkspec, data); in tegra20_clk_src_onecell_get()
1091 if (IS_ERR(clk)) in tegra20_clk_src_onecell_get()
1092 return clk; in tegra20_clk_src_onecell_get()
1094 hw = __clk_get_hw(clk); in tegra20_clk_src_onecell_get()
1098 * clock is created by the pinctrl driver. It is possible for clk user in tegra20_clk_src_onecell_get()
1103 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || in tegra20_clk_src_onecell_get()
1104 clkspec->args[0] == TEGRA20_CLK_CDEV2) { in tegra20_clk_src_onecell_get()
1107 return ERR_PTR(-EPROBE_DEFER); in tegra20_clk_src_onecell_get()
1110 if (clkspec->args[0] == TEGRA20_CLK_EMC) { in tegra20_clk_src_onecell_get()
1112 return ERR_PTR(-EPROBE_DEFER); in tegra20_clk_src_onecell_get()
1115 return clk; in tegra20_clk_src_onecell_get()
1160 CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
1173 struct clk *clk; in tegra20_car_probe() local
1175 clk = tegra_clk_register_super_mux("sclk", sclk_parents, in tegra20_car_probe()
1179 clks[TEGRA20_CLK_SCLK] = clk; in tegra20_car_probe()
1189 { .compatible = "nvidia,tegra20-car" },
1195 .name = "tegra20-car",