Lines Matching +full:0 +full:x4a0
17 #define AUDIO_SYNC_CLK_I2S0 0x4a0
18 #define AUDIO_SYNC_CLK_I2S1 0x4a4
19 #define AUDIO_SYNC_CLK_I2S2 0x4a8
20 #define AUDIO_SYNC_CLK_I2S3 0x4ac
21 #define AUDIO_SYNC_CLK_I2S4 0x4b0
22 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
23 #define AUDIO_SYNC_CLK_DMIC1 0x560
24 #define AUDIO_SYNC_CLK_DMIC2 0x564
25 #define AUDIO_SYNC_CLK_DMIC3 0x6b8
27 #define AUDIO_SYNC_DOUBLER 0x49c
29 #define PLLA_OUT 0xb4
140 for (i = 0, data = sync; i < num_sync_clks; i++, data++) { in tegra_audio_sync_clk_init()
148 clk_base + data->offset, 0, 3, 0, in tegra_audio_sync_clk_init()
157 0, clk_base + data->offset, 4, in tegra_audio_sync_clk_init()
178 for (i = 0; i < num_plls; i++) { in tegra_audio_clk_init()
184 clk_base, pmc_base, 0, info->pll_params, in tegra_audio_clk_init()
194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
197 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
198 CLK_SET_RATE_PARENT, 0, NULL); in tegra_audio_clk_init()
202 for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) { in tegra_audio_clk_init()
220 for (i = 0; i < ARRAY_SIZE(dmic_clks); i++) in tegra_audio_clk_init()
227 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) { in tegra_audio_clk_init()
239 0, 0, data->div_offset, 1, 0, in tegra_audio_clk_init()