1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
40 	val = readl_relaxed(mux->reg);  in clk_super_get_parent()
56 	if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&  in clk_super_get_parent()
57 	    (source == mux->pllx_index))  in clk_super_get_parent()
58 		source = mux->div2_index;  in clk_super_get_parent()
71 	if (mux->lock)  in clk_super_set_parent()
72 		spin_lock_irqsave(mux->lock, flags);  in clk_super_set_parent()
74 	val = readl_relaxed(mux->reg);  in clk_super_set_parent()
83 	 * For LP mode super-clock switch between PLLX direct  in clk_super_set_parent()
84 	 * and divided-by-2 outputs is allowed only when other  in clk_super_set_parent()
87 	if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||  in clk_super_set_parent()
88 					       (index == mux->pllx_index))) {  in clk_super_set_parent()
90 		if ((parent_index == mux->div2_index) ||  in clk_super_set_parent()
91 		    (parent_index == mux->pllx_index)) {  in clk_super_set_parent()
92 			err = -EINVAL;  in clk_super_set_parent()
97 		writel_relaxed(val, mux->reg);  in clk_super_set_parent()
100 		if (index == mux->div2_index)  in clk_super_set_parent()
101 			index = mux->pllx_index;  in clk_super_set_parent()
105 	if ((mux->flags & TEGRA210_CPU_CLK) &&  in clk_super_set_parent()
112 	writel_relaxed(val, mux->reg);  in clk_super_set_parent()
116 	if ((mux->flags & TEGRA210_CPU_CLK) &&  in clk_super_set_parent()
121 	if (mux->lock)  in clk_super_set_parent()
122 		spin_unlock_irqrestore(mux->lock, flags);  in clk_super_set_parent()
148 	struct clk_hw *div_hw = &super->frac_div.hw;  in clk_super_round_rate()
152 	return super->div_ops->round_rate(div_hw, rate, parent_rate);  in clk_super_round_rate()
159 	struct clk_hw *div_hw = &super->frac_div.hw;  in clk_super_recalc_rate()
163 	return super->div_ops->recalc_rate(div_hw, parent_rate);  in clk_super_recalc_rate()
170 	struct clk_hw *div_hw = &super->frac_div.hw;  in clk_super_set_rate()
174 	return super->div_ops->set_rate(div_hw, rate, parent_rate);  in clk_super_set_rate()
180 	struct clk_hw *div_hw = &super->frac_div.hw;  in clk_super_restore_context()
187 	super->div_ops->restore_context(div_hw);  in clk_super_restore_context()
202 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,  in tegra_clk_register_super_mux()  argument
207 	struct clk_init_data init;  in tegra_clk_register_super_mux()  local
211 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_super_mux()
213 	init.name = name;  in tegra_clk_register_super_mux()
214 	init.ops = &tegra_clk_super_mux_ops;  in tegra_clk_register_super_mux()
215 	init.flags = flags;  in tegra_clk_register_super_mux()
216 	init.parent_names = parent_names;  in tegra_clk_register_super_mux()
217 	init.num_parents = num_parents;  in tegra_clk_register_super_mux()
219 	super->reg = reg;  in tegra_clk_register_super_mux()
220 	super->pllx_index = pllx_index;  in tegra_clk_register_super_mux()
221 	super->div2_index = div2_index;  in tegra_clk_register_super_mux()
222 	super->lock = lock;  in tegra_clk_register_super_mux()
223 	super->width = width;  in tegra_clk_register_super_mux()
224 	super->flags = clk_super_flags;  in tegra_clk_register_super_mux()
226 	/* Data in .init is copied by clk_register(), so stack variable OK */  in tegra_clk_register_super_mux()
227 	super->hw.init = &init;  in tegra_clk_register_super_mux()
229 	clk = tegra_clk_dev_register(&super->hw);  in tegra_clk_register_super_mux()
238 		unsigned long flags, void __iomem *reg, u8 clk_super_flags,  in tegra_clk_register_super_clk()  argument
243 	struct clk_init_data init;  in tegra_clk_register_super_clk()  local
247 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_super_clk()
249 	init.name = name;  in tegra_clk_register_super_clk()
250 	init.ops = &tegra_clk_super_ops;  in tegra_clk_register_super_clk()
251 	init.flags = flags;  in tegra_clk_register_super_clk()
252 	init.parent_names = parent_names;  in tegra_clk_register_super_clk()
253 	init.num_parents = num_parents;  in tegra_clk_register_super_clk()
255 	super->reg = reg;  in tegra_clk_register_super_clk()
256 	super->lock = lock;  in tegra_clk_register_super_clk()
257 	super->width = 4;  in tegra_clk_register_super_clk()
258 	super->flags = clk_super_flags;  in tegra_clk_register_super_clk()
259 	super->frac_div.reg = reg + 4;  in tegra_clk_register_super_clk()
260 	super->frac_div.shift = 16;  in tegra_clk_register_super_clk()
261 	super->frac_div.width = 8;  in tegra_clk_register_super_clk()
262 	super->frac_div.frac_width = 1;  in tegra_clk_register_super_clk()
263 	super->frac_div.lock = lock;  in tegra_clk_register_super_clk()
264 	super->div_ops = &tegra_clk_frac_div_ops;  in tegra_clk_register_super_clk()
266 	/* Data in .init is copied by clk_register(), so stack variable OK */  in tegra_clk_register_super_clk()
267 	super->hw.init = &init;  in tegra_clk_register_super_clk()
269 	clk = clk_register(NULL, &super->hw);  in tegra_clk_register_super_clk()