1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 			     unsigned int *m, unsigned int *p)  in ccu_mp_find_best()  argument
28 			if ((rate - tmp_rate) < (rate - best_rate)) {  in ccu_mp_find_best()
36 	*m = best_m;  in ccu_mp_find_best()
56 	 * unsigned long in rate * m * p below  in ccu_mp_find_best_with_parent_adj()
103 	unsigned int m, p;  in ccu_mp_round_rate()  local
105 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_round_rate()
106 		rate *= cmp->fixed_post_div;  in ccu_mp_round_rate()
108 	max_m = cmp->m.max ?: 1 << cmp->m.width;  in ccu_mp_round_rate()
109 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);  in ccu_mp_round_rate()
111 	if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {  in ccu_mp_round_rate()
112 		ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);  in ccu_mp_round_rate()
113 		rate = *parent_rate / p / m;  in ccu_mp_round_rate()
119 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_round_rate()
120 		rate /= cmp->fixed_post_div;  in ccu_mp_round_rate()
129 	return ccu_gate_helper_disable(&cmp->common, cmp->enable);  in ccu_mp_disable()
136 	return ccu_gate_helper_enable(&cmp->common, cmp->enable);  in ccu_mp_enable()
143 	return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);  in ccu_mp_is_enabled()
151 	unsigned int m, p;  in ccu_mp_recalc_rate()  local
154 	/* Adjust parent_rate according to pre-dividers */  in ccu_mp_recalc_rate()
155 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,  in ccu_mp_recalc_rate()
158 	reg = readl(cmp->common.base + cmp->common.reg);  in ccu_mp_recalc_rate()
160 	m = reg >> cmp->m.shift;  in ccu_mp_recalc_rate()
161 	m &= (1 << cmp->m.width) - 1;  in ccu_mp_recalc_rate()
162 	m += cmp->m.offset;  in ccu_mp_recalc_rate()
163 	if (!m)  in ccu_mp_recalc_rate()
164 		m++;  in ccu_mp_recalc_rate()
166 	p = reg >> cmp->p.shift;  in ccu_mp_recalc_rate()
167 	p &= (1 << cmp->p.width) - 1;  in ccu_mp_recalc_rate()
169 	rate = (parent_rate >> p) / m;  in ccu_mp_recalc_rate()
170 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_recalc_rate()
171 		rate /= cmp->fixed_post_div;  in ccu_mp_recalc_rate()
181 	return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,  in ccu_mp_determine_rate()
191 	unsigned int m, p;  in ccu_mp_set_rate()  local
194 	/* Adjust parent_rate according to pre-dividers */  in ccu_mp_set_rate()
195 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,  in ccu_mp_set_rate()
198 	max_m = cmp->m.max ?: 1 << cmp->m.width;  in ccu_mp_set_rate()
199 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);  in ccu_mp_set_rate()
201 	/* Adjust target rate according to post-dividers */  in ccu_mp_set_rate()
202 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_set_rate()
203 		rate = rate * cmp->fixed_post_div;  in ccu_mp_set_rate()
205 	ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);  in ccu_mp_set_rate()
207 	spin_lock_irqsave(cmp->common.lock, flags);  in ccu_mp_set_rate()
209 	reg = readl(cmp->common.base + cmp->common.reg);  in ccu_mp_set_rate()
210 	reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);  in ccu_mp_set_rate()
211 	reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);  in ccu_mp_set_rate()
212 	reg |= (m - cmp->m.offset) << cmp->m.shift;  in ccu_mp_set_rate()
213 	reg |= ilog2(p) << cmp->p.shift;  in ccu_mp_set_rate()
215 	writel(reg, cmp->common.base + cmp->common.reg);  in ccu_mp_set_rate()
217 	spin_unlock_irqrestore(cmp->common.lock, flags);  in ccu_mp_set_rate()
226 	return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);  in ccu_mp_get_parent()
233 	return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);  in ccu_mp_set_parent()
251  * Support for MMC timing mode switching
255  * and set the timing mode on supported SoCs.
258  * takes in to account the timing mode switch. When the new timing
259  * mode is active, the clock output rate is halved. This new class
262  * if the new timing mode bit is set, to account for the post
264  * are halved if the mode bit is set.
272 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_recalc_rate()
283 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_determine_rate()
288 		req->rate *= 2;  in ccu_mp_mmc_determine_rate()
289 		req->min_rate *= 2;  in ccu_mp_mmc_determine_rate()
290 		req->max_rate *= 2;  in ccu_mp_mmc_determine_rate()
295 	/* re-adjust the requested clock rate back */  in ccu_mp_mmc_determine_rate()
297 		req->rate /= 2;  in ccu_mp_mmc_determine_rate()
298 		req->min_rate /= 2;  in ccu_mp_mmc_determine_rate()
299 		req->max_rate /= 2;  in ccu_mp_mmc_determine_rate()
309 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_set_rate()