Lines Matching +full:8 +full:m
31 * The M factor is present in the register's description, but not in the
32 * frequency formula, and it's documented as "M is only used for backdoor
39 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
53 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
54 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
68 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
69 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
85 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
103 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
104 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
121 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
122 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
139 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
140 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
157 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
158 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
172 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
173 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
187 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
188 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
208 { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
209 { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
215 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
216 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
233 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
240 0, 2, /* M */
241 8, 2, /* P */
249 0, 2, /* M */
250 8, 2, /* P */
255 0, 2, /* M */
256 8, 2, /* P */
261 0, 2, /* M */
262 8, 2, /* P */
269 0, 3, /* M */
276 0, 4, /* M */
289 0, 4, /* M */
310 0, 4, /* M */
311 8, 2, /* N */
321 0, 3, /* M */
330 0, 4, /* M */
331 8, 2, /* N */
341 0, 3, /* M */
397 0x804, BIT(8), 0);
408 0, 4, /* M */
409 8, 2, /* N */
415 0, 4, /* M */
416 8, 2, /* N */
426 0, 4, /* M */
427 8, 2, /* N */
434 0, 4, /* M */
435 8, 2, /* N */
442 0, 4, /* M */
443 8, 2, /* N */
467 0, 4, /* M */
468 8, 2, /* N */
474 0, 4, /* M */
475 8, 2, /* N */
487 0, 4, /* M */
488 8, 2, /* N */
497 0, 4, /* M */
498 8, 2, /* N */
510 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
523 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
536 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
549 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
567 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
582 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
597 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
611 * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
612 * We will force them to 0 (12M divided from 48M).
624 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
632 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
635 static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
637 static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
644 0, 4, /* M */
649 0, 5, /* M */
659 0, 4, /* M */
716 0, 4, /* M */
717 8, 2, /* P */
732 0, 4, /* M */
741 0, 5, /* M */
750 0, 4, /* M */
1199 val &= ~(GENMASK(15, 8) | BIT(0)); in sun50i_h6_ccu_probe()
1200 val |= 17 << 8; in sun50i_h6_ccu_probe()
1227 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) in sun50i_h6_ccu_probe()