Lines Matching +full:0 +full:xa9c
31 #define SUN50I_A100_PLL_PERIPH1_PATTERN0 0xd1303333
41 * testing", so it's not modelled and then force to 0.
43 #define SUN50I_A100_PLL_CPUX_REG 0x000
49 .reg = 0x000,
57 #define SUN50I_A100_PLL_DDR0_REG 0x010
63 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
65 .reg = 0x010,
73 #define SUN50I_A100_PLL_PERIPH0_REG 0x020
79 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
82 .reg = 0x020,
90 #define SUN50I_A100_PLL_PERIPH1_REG 0x028
96 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
99 .reg = 0x028,
106 #define SUN50I_A100_PLL_PERIPH1_PATTERN0_REG 0x128
108 #define SUN50I_A100_PLL_GPU_REG 0x030
114 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
116 .reg = 0x030,
125 * in the user manual. So it's not modelled and forced to 0.
127 #define SUN50I_A100_PLL_VIDEO0_REG 0x040
135 .reg = 0x040,
143 #define SUN50I_A100_PLL_VIDEO1_REG 0x048
151 .reg = 0x048,
159 #define SUN50I_A100_PLL_VIDEO2_REG 0x050
167 .reg = 0x050,
175 #define SUN50I_A100_PLL_VE_REG 0x058
181 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
183 .reg = 0x058,
195 #define SUN50I_A100_PLL_COM_REG 0x060
197 { .rate = 451584000, .pattern = 0xc0014396, .m = 2, .n = 37 },
204 .m = _SUNXI_CCU_DIV(0, 1),
206 0x160, BIT(31)),
208 .reg = 0x060,
216 #define SUN50I_A100_PLL_VIDEO3_REG 0x068
224 .reg = 0x068,
236 * Enforce the default for them, which is m0 = 1, m1 = 0.
238 #define SUN50I_A100_PLL_AUDIO_REG 0x078
240 { .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
241 { .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
242 { .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
243 { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
253 0x178, BIT(31)),
255 .reg = 0x078,
268 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
269 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
270 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
276 psi_ahb1_ahb2_parents, 0x510,
277 0, 2, /* M */
280 0);
286 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
287 0, 2, /* M */
290 0);
292 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
293 0, 2, /* M */
296 0);
298 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
299 0, 2, /* M */
302 0);
307 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
308 0, 3, /* M */
314 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de0", de_parents, 0x600,
315 0, 4, /* M */
321 0x60c, BIT(0), 0);
328 0x630,
329 0, 4, /* M */
332 0);
335 0x63c, BIT(0), 0);
338 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
339 0, 2, /* M */
342 0);
345 0x67c, BIT(0), 0);
348 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
349 0, 4, /* M */
353 0);
356 0x68c, BIT(0), 0);
359 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
360 0, 3, /* M */
366 0x69c, BIT(0), 0);
369 0x70c, BIT(0), 0);
372 0x71c, BIT(0), 0);
375 0x72c, BIT(0), 0);
378 0x73c, BIT(0), 0);
380 static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0);
383 0x78c, BIT(0), 0);
386 0x79c, BIT(0), 0);
388 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
390 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
393 0x804, BIT(0), 0);
395 0x804, BIT(1), 0);
397 0x804, BIT(2), 0);
399 0x804, BIT(5), 0);
401 0x804, BIT(8), 0);
403 0x804, BIT(9), 0);
405 0x804, BIT(10), 0);
408 0x80c, BIT(0), CLK_IS_CRITICAL);
415 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
416 0, 4, /* M */
420 0);
422 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
423 0, 4, /* M */
427 0);
429 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
433 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
434 0, 4, /* M */
441 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
442 0, 4, /* M */
449 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
450 0, 4, /* M */
457 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
458 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
459 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
461 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
462 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
463 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
464 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
465 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
467 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
468 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
469 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
470 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
472 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
473 0, 4, /* M */
477 0);
479 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
480 0, 4, /* M */
484 0);
486 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", nand_spi_parents, 0x948,
487 0, 4, /* M */
491 0);
493 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
494 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
495 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb3", 0x96c, BIT(2), 0);
497 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
498 BIT(31) | BIT(30), 0);
500 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
504 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_parents, 0x990,
505 0, 4, /* M */
509 0);
511 static SUNXI_CCU_GATE(bus_ir_rx_clk, "bus-ir-rx", "ahb3", 0x99c, BIT(0), 0);
513 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_parents, 0x9c0,
514 0, 4, /* M */
518 0);
520 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
522 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
524 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
532 .reg = 0xa10,
545 .reg = 0xa14,
558 .reg = 0xa18,
571 .reg = 0xa1c,
579 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa20, BIT(0), 0);
580 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa20, BIT(1), 0);
581 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa20, BIT(2), 0);
582 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa20, BIT(3), 0);
589 .reg = 0xa24,
593 0),
597 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
604 .reg = 0xa40,
608 0),
612 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
615 audio_parents, 0xa50,
616 0, 4, /* M */
619 0);
622 audio_parents, 0xa54,
623 0, 4, /* M */
626 0);
629 audio_parents, 0xa58,
630 0, 4, /* M */
633 0);
635 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
636 BIT(0), 0);
640 * We will force them to 0 (12M divided from 48M).
642 #define SUN50I_A100_USB0_CLK_REG 0xa70
643 #define SUN50I_A100_USB1_CLK_REG 0xa74
645 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
646 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "dcxo24M", 0xa70, BIT(29), 0);
648 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
649 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "dcxo24M", 0xa74, BIT(29), 0);
651 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
652 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
653 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
654 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
655 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
657 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "ahb3", 0xa9c, BIT(0), 0);
660 0xabc, BIT(0), 0);
663 0xacc, BIT(0), 0);
669 0xb24,
670 0, 4, /* M */
673 0);
676 0xb4c, BIT(0), 0);
684 tcon_lcd_parents, 0xb60,
685 0, 4, /* M */
689 0);
692 0xb7c, BIT(0), 0);
697 ledc_parents, 0xbf0,
698 0, 4, /* M */
702 0);
704 static SUNXI_CCU_GATE(bus_ledc_clk, "bus-ledc", "ahb3", 0xbfc, BIT(0), 0);
712 csi_top_parents, 0xc04,
713 0, 4, /* M */
716 0);
722 csi0_mclk_parents, 0xc08,
723 0, 5, /* M */
726 0);
732 csi1_mclk_parents, 0xc0c,
733 0, 5, /* M */
736 0);
738 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc1c, BIT(0), 0);
746 csi_isp_parents, 0xc20,
747 0, 5, /* M */
750 0);
753 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
761 1, 2, 0);
765 1, 2, 0);
1065 [RST_MBUS] = { 0x540, BIT(30) },
1067 [RST_BUS_DE] = { 0x60c, BIT(16) },
1068 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1069 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1070 [RST_BUS_CE] = { 0x68c, BIT(16) },
1071 [RST_BUS_VE] = { 0x69c, BIT(16) },
1072 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1073 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
1074 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1075 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1076 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1077 [RST_BUS_PSI] = { 0x79c, BIT(16) },
1078 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1079 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1080 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1081 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1082 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1083 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1084 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1085 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1086 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1087 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1088 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1089 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1090 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1091 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1092 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1093 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1094 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1095 [RST_BUS_SPI2] = { 0x96c, BIT(18) },
1096 [RST_BUS_EMAC] = { 0x97c, BIT(16) },
1097 [RST_BUS_IR_RX] = { 0x99c, BIT(16) },
1098 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1099 [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1100 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1101 [RST_BUS_I2S0] = { 0xa20, BIT(16) },
1102 [RST_BUS_I2S1] = { 0xa20, BIT(17) },
1103 [RST_BUS_I2S2] = { 0xa20, BIT(18) },
1104 [RST_BUS_I2S3] = { 0xa20, BIT(19) },
1105 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1106 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1107 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
1109 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1110 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1112 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1113 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1114 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1115 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1116 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1118 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1119 [RST_BUS_DPSS_TOP0] = { 0xabc, BIT(16) },
1120 [RST_BUS_DPSS_TOP1] = { 0xacc, BIT(16) },
1121 [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
1122 [RST_BUS_TCON_LCD] = { 0xb7c, BIT(16) },
1123 [RST_BUS_LVDS] = { 0xbac, BIT(16) },
1124 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1125 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1126 [RST_BUS_CSI_ISP] = { 0xc2c, BIT(16) },
1186 reg = devm_platform_ioremap_resource(pdev, 0); in sun50i_a100_ccu_probe()
1198 for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_regs); i++) { in sun50i_a100_ccu_probe()
1217 * Force the output divider of video PLLs to 0. in sun50i_a100_ccu_probe()
1221 for (i = 0; i < ARRAY_SIZE(sun50i_a100_pll_video_regs); i++) { in sun50i_a100_ccu_probe()
1223 val &= ~BIT(0); in sun50i_a100_ccu_probe()
1228 * Enforce m1 = 0, m0 = 1 for Audio PLL in sun50i_a100_ccu_probe()
1234 val |= BIT(0); in sun50i_a100_ccu_probe()
1243 for (i = 0; i < ARRAY_SIZE(sun50i_a100_usb2_clk_regs); i++) { in sun50i_a100_ccu_probe()
1260 return 0; in sun50i_a100_ccu_probe()