Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
26 #include "ccu-sun20i-d1.h"
38 .enable = BIT(27),
39 .lock = BIT(28),
43 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
52 .enable = BIT(27),
53 .lock = BIT(28),
59 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
67 .enable = BIT(27),
68 .lock = BIT(28),
73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
82 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
90 static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
94 static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
103 .enable = BIT(27),
104 .lock = BIT(28),
111 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-4x", osc24M,
120 static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
122 static CLK_FIXED_FACTOR_HWS(pll_video0_clk, "pll-video0",
127 .enable = BIT(27),
128 .lock = BIT(28),
135 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-4x", osc24M,
144 static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
146 static CLK_FIXED_FACTOR_HWS(pll_video1_clk, "pll-video1",
151 .enable = BIT(27),
152 .lock = BIT(28),
158 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
176 .enable = BIT(27),
177 .lock = BIT(28),
180 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
181 0x178, BIT(31)),
187 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x", osc24M,
196 static CLK_FIXED_FACTOR_HWS(pll_audio0_2x_clk, "pll-audio0-2x",
198 static CLK_FIXED_FACTOR_HWS(pll_audio0_clk, "pll-audio0",
202 * PLL_AUDIO1 doesn't need Fractional-N. The output is usually 614.4 MHz for
207 .enable = BIT(27),
208 .lock = BIT(28),
215 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio1", osc24M,
224 static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
226 static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
230 * The CPUX gate is not modelled - it is in a separate register (0x504)
243 0x500, 24, 3, CLK_SET_RATE_PARENT);
246 static SUNXI_CCU_M_HWS(cpux_axi_clk, "cpux-axi",
248 static SUNXI_CCU_M_HWS(cpux_apb_clk, "cpux-apb",
257 static SUNXI_CCU_MP_DATA_WITH_MUX(psi_ahb_clk, "psi-ahb", psi_ahb_parents, 0x510,
260 24, 2, /* mux */
272 24, 2, /* mux */
278 24, 2, /* mux */
293 24, 3, /* mux */
294 BIT(31), /* gate */
297 static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", psi_ahb_hws,
298 0x60c, BIT(0), 0);
302 24, 3, /* mux */
303 BIT(31), /* gate */
306 static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", psi_ahb_hws,
307 0x62c, BIT(0), 0);
311 24, 3, /* mux */
312 BIT(31), /* gate */
315 static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", psi_ahb_hws,
316 0x63c, BIT(0), 0);
326 24, 3, /* mux */
327 BIT(31), /* gate */
330 static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", psi_ahb_hws,
331 0x68c, BIT(0), 0);
339 24, 1, /* mux */
340 BIT(31), /* gate */
343 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", psi_ahb_hws,
344 0x69c, BIT(0), 0);
346 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", psi_ahb_hws,
347 0x70c, BIT(0), 0);
349 static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", psi_ahb_hws,
350 0x71c, BIT(0), 0);
351 static SUNXI_CCU_GATE_HWS(bus_msgbox1_clk, "bus-msgbox1", psi_ahb_hws,
352 0x71c, BIT(1), 0);
353 static SUNXI_CCU_GATE_HWS(bus_msgbox2_clk, "bus-msgbox2", psi_ahb_hws,
354 0x71c, BIT(2), 0);
356 static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", psi_ahb_hws,
357 0x72c, BIT(0), 0);
359 static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", psi_ahb_hws,
360 0x73c, BIT(0), 0);
363 0x740, BIT(31), 0);
365 static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", psi_ahb_hws,
366 0x78c, BIT(0), 0);
368 static SUNXI_CCU_GATE_HWS(bus_pwm_clk, "bus-pwm", apb0_hws,
369 0x7ac, BIT(0), 0);
371 static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws,
372 0x7bc, BIT(0), 0);
383 24, 2, /* mux */
384 BIT(31), CLK_IS_CRITICAL);
391 static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
392 0x804, BIT(0), 0);
393 static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
394 0x804, BIT(1), 0);
395 static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
396 0x804, BIT(2), 0);
397 static SUNXI_CCU_GATE_HWS(mbus_tvin_clk, "mbus-tvin", mbus_hws,
398 0x804, BIT(7), 0);
399 static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
400 0x804, BIT(8), 0);
401 static SUNXI_CCU_GATE_HWS(mbus_g2d_clk, "mbus-g2d", mbus_hws,
402 0x804, BIT(10), 0);
403 static SUNXI_CCU_GATE_HWS(mbus_riscv_clk, "mbus-riscv", mbus_hws,
404 0x804, BIT(11), 0);
406 static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", psi_ahb_hws,
407 0x80c, BIT(0), CLK_IS_CRITICAL);
418 24, 3, /* mux */
419 BIT(31), /* gate */
425 24, 3, /* mux */
426 BIT(31), /* gate */
439 24, 3, /* mux */
440 BIT(31), /* gate */
443 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,
444 0x84c, BIT(0), 0);
445 static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", psi_ahb_hws,
446 0x84c, BIT(1), 0);
447 static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", psi_ahb_hws,
448 0x84c, BIT(2), 0);
450 static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws,
451 0x90c, BIT(0), 0);
452 static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws,
453 0x90c, BIT(1), 0);
454 static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws,
455 0x90c, BIT(2), 0);
456 static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws,
457 0x90c, BIT(3), 0);
458 static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws,
459 0x90c, BIT(4), 0);
460 static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws,
461 0x90c, BIT(5), 0);
463 static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws,
464 0x91c, BIT(0), 0);
465 static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws,
466 0x91c, BIT(1), 0);
467 static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws,
468 0x91c, BIT(2), 0);
469 static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws,
470 0x91c, BIT(3), 0);
482 24, 3, /* mux */
483 BIT(31), /* gate */
489 24, 3, /* mux */
490 BIT(31), /* gate */
493 static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", psi_ahb_hws,
494 0x96c, BIT(0), 0);
495 static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", psi_ahb_hws,
496 0x96c, BIT(1), 0);
498 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25M_clk, "emac-25M", pll_periph0_hws,
499 0x970, BIT(31) | BIT(30), 24, 0);
501 static SUNXI_CCU_GATE_HWS(bus_emac_clk, "bus-emac", psi_ahb_hws,
502 0x97c, BIT(0), 0);
508 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 0x9c0,
511 24, 3, /* mux */
512 BIT(31), /* gate */
515 static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws,
516 0x9cc, BIT(0), 0);
518 static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", apb0_hws,
519 0x9ec, BIT(0), 0);
521 static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws,
522 0x9fc, BIT(0), 0);
533 24, 3, /* mux */
534 BIT(31), /* gate */
540 24, 3, /* mux */
541 BIT(31), /* gate */
547 24, 3, /* mux */
548 BIT(31), /* gate */
557 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c,
560 24, 3, /* mux */
561 BIT(31), /* gate */
564 static SUNXI_CCU_GATE_HWS(bus_i2s0_clk, "bus-i2s0", apb0_hws,
565 0xa20, BIT(0), 0);
566 static SUNXI_CCU_GATE_HWS(bus_i2s1_clk, "bus-i2s1", apb0_hws,
567 0xa20, BIT(1), 0);
568 static SUNXI_CCU_GATE_HWS(bus_i2s2_clk, "bus-i2s2", apb0_hws,
569 0xa20, BIT(2), 0);
571 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24,
574 24, 3, /* mux */
575 BIT(31), /* gate */
583 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28,
586 24, 3, /* mux */
587 BIT(31), /* gate */
590 static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb0_hws,
591 0xa2c, BIT(0), 0);
601 24, 3, /* mux */
602 BIT(31), /* gate */
605 static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb0_hws,
606 0xa4c, BIT(0), 0);
608 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_dac_clk, "audio-dac", dmic_codec_parents, 0xa50,
611 24, 3, /* mux */
612 BIT(31), /* gate */
615 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_adc_clk, "audio-adc", dmic_codec_parents, 0xa54,
618 24, 3, /* mux */
619 BIT(31), /* gate */
622 static SUNXI_CCU_GATE_HWS(bus_audio_clk, "bus-audio", apb0_hws,
623 0xa5c, BIT(0), 0);
628 * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
642 .enable = BIT(31),
644 .shift = 24,
652 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
660 .enable = BIT(31),
662 .shift = 24,
670 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
677 static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", psi_ahb_hws,
678 0xa8c, BIT(0), 0);
679 static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", psi_ahb_hws,
680 0xa8c, BIT(1), 0);
681 static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", psi_ahb_hws,
682 0xa8c, BIT(4), 0);
683 static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", psi_ahb_hws,
684 0xa8c, BIT(5), 0);
685 static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", psi_ahb_hws,
686 0xa8c, BIT(8), 0);
688 static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws,
689 0xa9c, BIT(0), 0);
691 static SUNXI_CCU_GATE_HWS(bus_dpss_top_clk, "bus-dpss-top", psi_ahb_hws,
692 0xabc, BIT(0), 0);
694 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M,
695 0xb04, BIT(31), 0);
697 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
699 0xb10, BIT(30), 36621, 0);
705 static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0xb10,
706 24, 1, /* mux */
707 BIT(31), /* gate */
710 static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", psi_ahb_hws,
711 0xb1c, BIT(0), 0);
720 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24,
722 24, 3, /* mux */
723 BIT(31), /* gate */
726 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi_clk, "bus-mipi-dsi", psi_ahb_hws,
727 0xb4c, BIT(0), 0);
737 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_tve_parents, 0xb60,
740 24, 3, /* mux */
741 BIT(31), /* gate */
744 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", psi_ahb_hws,
745 0xb7c, BIT(0), 0);
747 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv", tcon_tve_parents, 0xb80,
750 24, 3, /* mux */
751 BIT(31), /* gate */
754 static SUNXI_CCU_GATE_HWS(bus_tcon_tv_clk, "bus-tcon-tv", psi_ahb_hws,
755 0xb9c, BIT(0), 0);
760 24, 3, /* mux */
761 BIT(31), /* gate */
764 static SUNXI_CCU_GATE_HWS(bus_tve_top_clk, "bus-tve-top", psi_ahb_hws,
765 0xbbc, BIT(0), 0);
766 static SUNXI_CCU_GATE_HWS(bus_tve_clk, "bus-tve", psi_ahb_hws,
767 0xbbc, BIT(1), 0);
777 24, 3, /* mux */
778 BIT(31), /* gate */
781 static SUNXI_CCU_GATE_HWS(bus_tvd_top_clk, "bus-tvd-top", psi_ahb_hws,
782 0xbdc, BIT(0), 0);
783 static SUNXI_CCU_GATE_HWS(bus_tvd_clk, "bus-tvd", psi_ahb_hws,
784 0xbdc, BIT(1), 0);
789 24, 1, /* mux */
790 BIT(31), /* gate */
793 static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", psi_ahb_hws,
794 0xbfc, BIT(0), 0);
801 static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
803 24, 3, /* mux */
804 BIT(31), /* gate */
815 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0xc08,
817 24, 3, /* mux */
818 BIT(31), /* gate */
821 static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", psi_ahb_hws,
822 0xc1c, BIT(0), 0);
829 24, 3, /* mux */
830 BIT(31), /* gate */
833 static SUNXI_CCU_GATE_HWS(bus_tpadc_clk, "bus-tpadc", apb0_hws,
834 0xc5c, BIT(0), 0);
836 static SUNXI_CCU_GATE_HWS(bus_tzma_clk, "bus-tzma", apb0_hws,
837 0xc6c, BIT(0), 0);
848 24, 3, /* mux */
849 BIT(31), /* gate */
852 static SUNXI_CCU_GATE_HWS(bus_dsp_cfg_clk, "bus-dsp-cfg", psi_ahb_hws,
853 0xc7c, BIT(1), 0);
856 * The RISC-V gate is not modelled - it is in a separate register (0xd04)
870 24, 3, /* mux */
873 /* The riscv-axi clk must be divided by at least 2. */
880 static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
883 static SUNXI_CCU_GATE_HWS(bus_riscv_cfg_clk, "bus-riscv-cfg", psi_ahb_hws,
884 0xd0c, BIT(0), CLK_IS_CRITICAL);
886 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
887 0xf30, BIT(0), 0);
888 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
889 0xf30, BIT(1), 2, 0);
890 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_2x_hws,
891 0xf30, BIT(2), 75, 0);
892 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_hws,
893 0xf30, BIT(3), 24, 0);
894 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_32k_clk, "fanout-32k", pll_periph0_2x_hws,
895 0xf30, BIT(4), 36621, 0);
903 static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
905 24, 2, /* mux */
906 BIT(31), /* gate */
909 static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
911 BIT(31), /* gate */
925 BIT(21), /* gate */
929 BIT(22), /* gate */
933 BIT(23), /* gate */
1227 [RST_MBUS] = { 0x540, BIT(30) },
1228 [RST_BUS_DE] = { 0x60c, BIT(16) },
1229 [RST_BUS_DI] = { 0x62c, BIT(16) },
1230 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1231 [RST_BUS_CE] = { 0x68c, BIT(16) },
1232 [RST_BUS_VE] = { 0x69c, BIT(16) },
1233 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1234 [RST_BUS_MSGBOX0] = { 0x71c, BIT(16) },
1235 [RST_BUS_MSGBOX1] = { 0x71c, BIT(17) },
1236 [RST_BUS_MSGBOX2] = { 0x71c, BIT(18) },
1237 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1238 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1239 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1240 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1241 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1242 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1243 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1244 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1245 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1246 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1247 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1248 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1249 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1250 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1251 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1252 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1253 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1254 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1255 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1256 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1257 [RST_BUS_EMAC] = { 0x97c, BIT(16) },
1258 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1259 [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1260 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1261 [RST_BUS_I2S0] = { 0xa20, BIT(16) },
1262 [RST_BUS_I2S1] = { 0xa20, BIT(17) },
1263 [RST_BUS_I2S2] = { 0xa20, BIT(18) },
1264 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1265 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1266 [RST_BUS_AUDIO] = { 0xa5c, BIT(16) },
1267 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1268 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1269 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1270 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1271 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1272 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1273 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1274 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1275 [RST_BUS_DPSS_TOP] = { 0xabc, BIT(16) },
1276 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1277 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1278 [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
1279 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1280 [RST_BUS_TCON_TV] = { 0xb9c, BIT(16) },
1281 [RST_BUS_LVDS0] = { 0xbac, BIT(16) },
1282 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1283 [RST_BUS_TVE] = { 0xbbc, BIT(17) },
1284 [RST_BUS_TVD_TOP] = { 0xbdc, BIT(16) },
1285 [RST_BUS_TVD] = { 0xbdc, BIT(17) },
1286 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1287 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1288 [RST_BUS_TPADC] = { 0xc5c, BIT(16) },
1289 [RST_DSP] = { 0xc7c, BIT(16) },
1290 [RST_BUS_DSP_CFG] = { 0xc7c, BIT(17) },
1291 [RST_BUS_DSP_DBG] = { 0xc7c, BIT(18) },
1292 [RST_BUS_RISCV_CFG] = { 0xd0c, BIT(16) },
1325 .bypass_index = 4, /* index of pll-periph0 */
1341 val |= BIT(31) | BIT(30) | BIT(29); in sun20i_d1_ccu_probe()
1353 * See the comment before pll-video0 definition for the reason. in sun20i_d1_ccu_probe()
1357 val &= ~BIT(0); in sun20i_d1_ccu_probe()
1363 val &= ~BIT(1) | BIT(0); in sun20i_d1_ccu_probe()
1366 /* Force fanout-27M factor N to 0. */ in sun20i_d1_ccu_probe()
1371 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_ccu_desc); in sun20i_d1_ccu_probe()
1383 { .compatible = "allwinner,sun20i-d1-ccu" },
1390 .name = "sun20i-d1-ccu",