Lines Matching +full:0 +full:xa9c
34 * in the user manual. So it's not modelled and forced to 0.
36 #define SUN20I_D1_PLL_CPUX_REG 0x000
42 .reg = 0x000,
50 #define SUN20I_D1_PLL_DDR0_REG 0x010
56 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
58 .reg = 0x010,
65 #define SUN20I_D1_PLL_PERIPH0_REG 0x020
72 .reg = 0x020,
83 pll_periph0_4x_hws, 0x020, 16, 3, 0);
85 pll_periph0_4x_hws, 0x020, 20, 3, 0);
91 pll_periph0_2x_hws, 2, 1, 0);
95 pll_periph0_2x_hws, 6, 1, 0);
99 * in the user manual. So it's not modelled and forced to 0.
101 #define SUN20I_D1_PLL_VIDEO0_REG 0x040
110 .reg = 0x040,
125 #define SUN20I_D1_PLL_VIDEO1_REG 0x048
134 .reg = 0x048,
149 #define SUN20I_D1_PLL_VE_REG 0x058
155 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
157 .reg = 0x058,
167 * ignore them for now. Enforce the default for them, which is m1 = 0, m0 = 0.
170 #define SUN20I_D1_PLL_AUDIO0_REG 0x078
172 { .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
181 0x178, BIT(31)),
185 .reg = 0x078,
197 pll_audio0_4x_hws, 2, 1, 0);
199 pll_audio0_4x_hws, 4, 1, 0);
205 #define SUN20I_D1_PLL_AUDIO1_REG 0x080
214 .reg = 0x080,
225 pll_audio1_hws, 0x080, 16, 3, 0);
227 pll_audio1_hws, 0x080, 20, 3, 0);
230 * The CPUX gate is not modelled - it is in a separate register (0x504)
243 0x500, 24, 3, CLK_SET_RATE_PARENT);
247 cpux_hws, 0x500, 0, 2, 0);
249 cpux_hws, 0x500, 8, 2, 0);
257 static SUNXI_CCU_MP_DATA_WITH_MUX(psi_ahb_clk, "psi-ahb", psi_ahb_parents, 0x510,
258 0, 2, /* M */
261 0);
269 static SUNXI_CCU_MP_DATA_WITH_MUX(apb0_clk, "apb0", apb0_apb1_parents, 0x520,
270 0, 5, /* M */
273 0);
275 static SUNXI_CCU_MP_DATA_WITH_MUX(apb1_clk, "apb1", apb0_apb1_parents, 0x524,
276 0, 5, /* M */
279 0);
291 static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_di_g2d_parents, 0x600,
292 0, 5, /* M */
298 0x60c, BIT(0), 0);
300 static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
301 0, 5, /* M */
307 0x62c, BIT(0), 0);
309 static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", de_di_g2d_parents, 0x630,
310 0, 5, /* M */
313 0);
316 0x63c, BIT(0), 0);
323 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
324 0, 4, /* M */
328 0);
331 0x68c, BIT(0), 0);
337 static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
338 0, 5, /* M */
344 0x69c, BIT(0), 0);
347 0x70c, BIT(0), 0);
350 0x71c, BIT(0), 0);
352 0x71c, BIT(1), 0);
354 0x71c, BIT(2), 0);
357 0x72c, BIT(0), 0);
360 0x73c, BIT(0), 0);
363 0x740, BIT(31), 0);
366 0x78c, BIT(0), 0);
369 0x7ac, BIT(0), 0);
372 0x7bc, BIT(0), 0);
380 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x800,
381 0, 2, /* M */
387 &dram_clk.common.hw, 4, 1, 0);
392 0x804, BIT(0), 0);
394 0x804, BIT(1), 0);
396 0x804, BIT(2), 0);
398 0x804, BIT(7), 0);
400 0x804, BIT(8), 0);
402 0x804, BIT(10), 0);
404 0x804, BIT(11), 0);
407 0x80c, BIT(0), CLK_IS_CRITICAL);
415 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
416 0, 4, /* M */
420 0);
422 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
423 0, 4, /* M */
427 0);
436 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
437 0, 4, /* M */
441 0);
444 0x84c, BIT(0), 0);
446 0x84c, BIT(1), 0);
448 0x84c, BIT(2), 0);
451 0x90c, BIT(0), 0);
453 0x90c, BIT(1), 0);
455 0x90c, BIT(2), 0);
457 0x90c, BIT(3), 0);
459 0x90c, BIT(4), 0);
461 0x90c, BIT(5), 0);
464 0x91c, BIT(0), 0);
466 0x91c, BIT(1), 0);
468 0x91c, BIT(2), 0);
470 0x91c, BIT(3), 0);
479 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
480 0, 4, /* M */
484 0);
486 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
487 0, 4, /* M */
491 0);
494 0x96c, BIT(0), 0);
496 0x96c, BIT(1), 0);
499 0x970, BIT(31) | BIT(30), 24, 0);
502 0x97c, BIT(0), 0);
508 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 0x9c0,
509 0, 4, /* M */
513 0);
516 0x9cc, BIT(0), 0);
519 0x9ec, BIT(0), 0);
522 0x9fc, BIT(0), 0);
530 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s0_clk, "i2s0", i2s_spdif_tx_parents, 0xa10,
531 0, 5, /* M */
535 0);
537 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s1_clk, "i2s1", i2s_spdif_tx_parents, 0xa14,
538 0, 5, /* M */
542 0);
544 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_clk, "i2s2", i2s_spdif_tx_parents, 0xa18,
545 0, 5, /* M */
549 0);
557 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c,
558 0, 5, /* M */
562 0);
565 0xa20, BIT(0), 0);
567 0xa20, BIT(1), 0);
569 0xa20, BIT(2), 0);
571 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24,
572 0, 5, /* M */
576 0);
583 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28,
584 0, 5, /* M */
588 0);
591 0xa2c, BIT(0), 0);
598 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_codec_parents, 0xa40,
599 0, 5, /* M */
603 0);
606 0xa4c, BIT(0), 0);
608 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_dac_clk, "audio-dac", dmic_codec_parents, 0xa50,
609 0, 5, /* M */
613 0);
615 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(audio_adc_clk, "audio-adc", dmic_codec_parents, 0xa54,
616 0, 5, /* M */
620 0);
623 0xa5c, BIT(0), 0);
637 { .index = 0, .div = 50 },
650 .reg = 0xa70,
655 0),
668 .reg = 0xa74,
673 0),
678 0xa8c, BIT(0), 0);
680 0xa8c, BIT(1), 0);
682 0xa8c, BIT(4), 0);
684 0xa8c, BIT(5), 0);
686 0xa8c, BIT(8), 0);
689 0xa9c, BIT(0), 0);
692 0xabc, BIT(0), 0);
695 0xb04, BIT(31), 0);
699 0xb10, BIT(30), 36621, 0);
705 static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0xb10,
708 0);
711 0xb1c, BIT(0), 0);
720 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", mipi_dsi_parents, 0xb24,
721 0, 4, /* M */
727 0xb4c, BIT(0), 0);
737 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_tve_parents, 0xb60,
738 0, 4, /* M */
745 0xb7c, BIT(0), 0);
747 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv", tcon_tve_parents, 0xb80,
748 0, 4, /* M */
755 0xb9c, BIT(0), 0);
757 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tve_clk, "tve", tcon_tve_parents, 0xbb0,
758 0, 4, /* M */
762 0);
765 0xbbc, BIT(0), 0);
767 0xbbc, BIT(1), 0);
775 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents, 0xbc0,
776 0, 5, /* M */
779 0);
782 0xbdc, BIT(0), 0);
784 0xbdc, BIT(1), 0);
786 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents, 0xbf0,
787 0, 4, /* M */
791 0);
794 0xbfc, BIT(0), 0);
801 static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 0xc04,
802 0, 4, /* M */
805 0);
815 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0xc08,
816 0, 5, /* M */
819 0);
822 0xc1c, BIT(0), 0);
828 static SUNXI_CCU_MUX_DATA_WITH_GATE(tpadc_clk, "tpadc", tpadc_parents, 0xc50,
831 0);
834 0xc5c, BIT(0), 0);
837 0xc6c, BIT(0), 0);
846 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
847 0, 5, /* M */
850 0);
853 0xc7c, BIT(1), 0);
856 * The RISC-V gate is not modelled - it is in a separate register (0xd04)
868 static SUNXI_CCU_M_DATA_WITH_MUX(riscv_clk, "riscv", riscv_parents, 0xd00,
869 0, 5, /* M */
881 0xd00, 8, 2, riscv_axi_table, 0);
884 0xd0c, BIT(0), CLK_IS_CRITICAL);
887 0xf30, BIT(0), 0);
889 0xf30, BIT(1), 2, 0);
891 0xf30, BIT(2), 75, 0);
893 0xf30, BIT(3), 24, 0);
895 0xf30, BIT(4), 36621, 0);
897 /* This clock has a second divider that is not modelled and forced to 0. */
898 #define SUN20I_D1_FANOUT_27M_REG 0xf34
903 static SUNXI_CCU_M_HW_WITH_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0xf34,
904 0, 5, /* M */
907 0);
909 static SUNXI_CCU_M_HWS_WITH_GATE(fanout_pclk_clk, "fanout-pclk", apb0_hws, 0xf38,
910 0, 5, /* M */
912 0);
923 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0xf3c,
924 0, 3, /* mux */
926 0);
927 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0xf3c,
930 0);
931 static SUNXI_CCU_MUX_HW_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0xf3c,
934 0);
1227 [RST_MBUS] = { 0x540, BIT(30) },
1228 [RST_BUS_DE] = { 0x60c, BIT(16) },
1229 [RST_BUS_DI] = { 0x62c, BIT(16) },
1230 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1231 [RST_BUS_CE] = { 0x68c, BIT(16) },
1232 [RST_BUS_VE] = { 0x69c, BIT(16) },
1233 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1234 [RST_BUS_MSGBOX0] = { 0x71c, BIT(16) },
1235 [RST_BUS_MSGBOX1] = { 0x71c, BIT(17) },
1236 [RST_BUS_MSGBOX2] = { 0x71c, BIT(18) },
1237 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1238 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1239 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1240 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1241 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1242 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1243 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1244 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1245 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1246 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1247 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1248 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1249 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1250 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1251 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1252 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1253 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1254 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1255 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1256 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1257 [RST_BUS_EMAC] = { 0x97c, BIT(16) },
1258 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1259 [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1260 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1261 [RST_BUS_I2S0] = { 0xa20, BIT(16) },
1262 [RST_BUS_I2S1] = { 0xa20, BIT(17) },
1263 [RST_BUS_I2S2] = { 0xa20, BIT(18) },
1264 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1265 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1266 [RST_BUS_AUDIO] = { 0xa5c, BIT(16) },
1267 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1268 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1269 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1270 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1271 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1272 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1273 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1274 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1275 [RST_BUS_DPSS_TOP] = { 0xabc, BIT(16) },
1276 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1277 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1278 [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
1279 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1280 [RST_BUS_TCON_TV] = { 0xb9c, BIT(16) },
1281 [RST_BUS_LVDS0] = { 0xbac, BIT(16) },
1282 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1283 [RST_BUS_TVE] = { 0xbbc, BIT(17) },
1284 [RST_BUS_TVD_TOP] = { 0xbdc, BIT(16) },
1285 [RST_BUS_TVD] = { 0xbdc, BIT(17) },
1286 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1287 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1288 [RST_BUS_TPADC] = { 0xc5c, BIT(16) },
1289 [RST_DSP] = { 0xc7c, BIT(16) },
1290 [RST_BUS_DSP_CFG] = { 0xc7c, BIT(17) },
1291 [RST_BUS_DSP_DBG] = { 0xc7c, BIT(18) },
1292 [RST_BUS_RISCV_CFG] = { 0xd0c, BIT(16) },
1334 reg = devm_platform_ioremap_resource(pdev, 0); in sun20i_d1_ccu_probe()
1339 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun20i_d1_ccu_probe()
1345 /* Force PLL_CPUX factor M to 0. */ in sun20i_d1_ccu_probe()
1347 val &= ~GENMASK(1, 0); in sun20i_d1_ccu_probe()
1351 * Force the output divider of video PLLs to 0. in sun20i_d1_ccu_probe()
1355 for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) { in sun20i_d1_ccu_probe()
1357 val &= ~BIT(0); in sun20i_d1_ccu_probe()
1361 /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */ in sun20i_d1_ccu_probe()
1363 val &= ~BIT(1) | BIT(0); in sun20i_d1_ccu_probe()
1366 /* Force fanout-27M factor N to 0. */ in sun20i_d1_ccu_probe()
1379 return 0; in sun20i_d1_ccu_probe()