Lines Matching refs:div_id
207 u16 div_id, in stm32_divider_get_rate() argument
210 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_get_rate()
221 div_id); in stm32_divider_get_rate()
230 u16 div_id, unsigned long rate, in stm32_divider_set_rate() argument
233 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_set_rate()
339 if (div->div_id == NO_STM32_DIV) in clk_stm32_divider_set_rate()
344 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate); in clk_stm32_divider_set_rate()
357 if (div->div_id == NO_STM32_DIV) in clk_stm32_divider_round_rate()
360 divider = &div->clock_data->dividers[div->div_id]; in clk_stm32_divider_round_rate()
384 if (div->div_id == NO_STM32_DIV) in clk_stm32_divider_recalc_rate()
387 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate); in clk_stm32_divider_recalc_rate()
403 if (composite->div_id == NO_STM32_DIV) in clk_stm32_composite_set_rate()
409 composite->div_id, rate, parent_rate); in clk_stm32_composite_set_rate()
421 if (composite->div_id == NO_STM32_DIV) in clk_stm32_composite_recalc_rate()
425 composite->div_id, parent_rate); in clk_stm32_composite_recalc_rate()
435 if (composite->div_id == NO_STM32_DIV) in clk_stm32_composite_round_rate()
438 divider = &composite->clock_data->dividers[composite->div_id]; in clk_stm32_composite_round_rate()