26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
37 #define C28_NDIV_MASK (0xff)
38 #define C28_IDF_MASK (0x7)
39 #define C28_ODF_MASK (0x3f)
77 	.pdn_status	= CLKGEN_FIELD(0x2a0,	0x1,			8),
78 	.pdn_ctrl	= CLKGEN_FIELD(0x2a0,	0x1,			8),
79 	.locked_status	= CLKGEN_FIELD(0x2a0,	0x1,			24),
80 	.ndiv		= CLKGEN_FIELD(0x2a4,	C32_NDIV_MASK,		16),
81 	.idf		= CLKGEN_FIELD(0x2a4,	C32_IDF_MASK,		0x0),
83 	.odf		= { CLKGEN_FIELD(0x2b4, C32_ODF_MASK,		0) },
84 	.odf_gate	= { CLKGEN_FIELD(0x2b4, 0x1,			6) },
93 	{ .name = "clk-s-a0-pll-odf-0", },
102 	{ .name = "clk-s-c0-pll0-odf-0", },
112 	.pdn_status	= CLKGEN_FIELD(0x2c8,	0x1,			8),
113 	.pdn_ctrl	= CLKGEN_FIELD(0x2c8,	0x1,			8),
114 	.locked_status	= CLKGEN_FIELD(0x2c8,	0x1,			24),
115 	.ndiv		= CLKGEN_FIELD(0x2cc,	C32_NDIV_MASK,		16),
116 	.idf		= CLKGEN_FIELD(0x2cc,	C32_IDF_MASK,		0x0),
118 	.odf		= { CLKGEN_FIELD(0x2dc, C32_ODF_MASK,		0) },
119 	.odf_gate	= { CLKGEN_FIELD(0x2dc, 0x1,			6) },
128 	{ .name = "clk-s-c0-pll1-odf-0", },
138 	.pdn_status	= CLKGEN_FIELD(0x1a8,	0x1,			0),
139 	.pdn_ctrl	= CLKGEN_FIELD(0x1a8,	0x1,			0),
140 	.locked_status	= CLKGEN_FIELD(0x87c,	0x1,			0),
141 	.ndiv		= CLKGEN_FIELD(0x1b0,	C32_NDIV_MASK,		0),
142 	.idf		= CLKGEN_FIELD(0x1a8,	C32_IDF_MASK,		25),
144 	.odf		= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK,		8) },
145 	.odf_gate	= { CLKGEN_FIELD(0x1ac, 0x1,			28) },
147 	.cp		= CLKGEN_FIELD(0x1a8,	C32_CP_MASK,		1),
148 	.switch2pll	= CLKGEN_FIELD(0x1a4,	0x1,			1),
164 	.pdn_status	= CLKGEN_FIELD(0x1a8,	0x1,			0),
165 	.pdn_ctrl	= CLKGEN_FIELD(0x1a8,	0x1,			0),
166 	.locked_status	= CLKGEN_FIELD(0x87c,	0x1,			0),
167 	.ndiv		= CLKGEN_FIELD(0x1b0,	C28_NDIV_MASK,		0),
168 	.idf		= CLKGEN_FIELD(0x1a8,	C28_IDF_MASK,		25),
170 	.odf		= { CLKGEN_FIELD(0x1b0, C28_ODF_MASK,		8) },
171 	.odf_gate	= { CLKGEN_FIELD(0x1ac, 0x1,			28) },
173 	.switch2pll	= CLKGEN_FIELD(0x1a4,	0x1,			1),
248 	int ret = 0;  in __clkgen_pll_enable()
252 		return 0;  in __clkgen_pll_enable()
254 	CLKGEN_WRITE(pll, pdn_ctrl, 0);  in __clkgen_pll_enable()
257 			!!((reg >> field->shift) & field->mask),  0, 10000);  in __clkgen_pll_enable()
261 			CLKGEN_WRITE(pll, switch2pll, 0);  in __clkgen_pll_enable()
272 	unsigned long flags = 0;  in clkgen_pll_enable()
273 	int ret = 0;  in clkgen_pll_enable()
304 	unsigned long flags = 0;  in clkgen_pll_disable()
319 	unsigned long deviation = ~0;  in clk_pll3200c32_get_params()
355 	if (deviation == ~0) /* No solution found */  in clk_pll3200c32_get_params()
362 	return 0;  in clk_pll3200c32_get_params()
373 	return 0;  in clk_pll3200c32_get_rate()
381 	unsigned long rate = 0;  in recalc_stm_pll3200c32()
384 		return 0;  in recalc_stm_pll3200c32()
408 		return 0;  in round_rate_stm_pll3200c32()
424 	long hwrate = 0;  in set_rate_stm_pll3200c32()
425 	unsigned long flags = 0;  in set_rate_stm_pll3200c32()
433 	pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",  in set_rate_stm_pll3200c32()
459 	return 0;  in set_rate_stm_pll3200c32()
481 	unsigned long deviation = ~0;  in clk_pll4600c28_get_params()
515 	if (deviation == ~0) /* No solution found */  in clk_pll4600c28_get_params()
518 	return 0;  in clk_pll4600c28_get_params()
529 	return 0;  in clk_pll4600c28_get_rate()
540 		return 0;  in recalc_stm_pll4600c28()
562 		return 0;  in round_rate_stm_pll4600c28()
579 	unsigned long flags = 0;  in set_rate_stm_pll4600c28()
592 	pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",  in set_rate_stm_pll4600c28()
616 	return 0;  in set_rate_stm_pll4600c28()
693 	reg = of_iomap(pnode, 0);  in clkgen_get_register_base()
758 	unsigned long pll_flags = 0;  in clkgen_c32_pll_setup()
761 	parent_name = of_clk_get_parent_name(np, 0);  in clkgen_c32_pll_setup()
769 	of_clk_detect_critical(np, 0, &pll_flags);  in clkgen_c32_pll_setup()
791 	for (odf = 0; odf < num_odfs; odf++) {  in clkgen_c32_pll_setup()
794 		unsigned long odf_flags = 0;  in clkgen_c32_pll_setup()