Lines Matching +full:400 +full:khz
168 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
180 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
191 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
203 * 250, 332, 400 or 500 MHz considering different possibilites of input
209 * 400 200 100 0x04000
210 * 400 250 125 0x03333
211 * 400 332 166 0x0268D
212 * 400 400 200 0x02000
217 * 500 400 200 0x02800
223 * 600 400 200 0x03000
229 * 664 400 200 0x0351E
235 * 800 400 200 0x04000
351 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
352 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
353 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
354 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
357 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
358 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
363 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
364 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
460 /* clock derived from 32 KHz osc clk */ in spear1340_clk_init()