Lines Matching +full:0 +full:x02000
20 #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
27 #define SPEAR1340_PLL_CFG (misc_base + 0x210)
39 #define SPEAR1340_PLL1_CTR (misc_base + 0x214)
40 #define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
41 #define SPEAR1340_PLL2_CTR (misc_base + 0x220)
42 #define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
43 #define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
44 #define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
45 #define SPEAR1340_PLL4_CTR (misc_base + 0x238)
46 #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
47 #define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244)
65 #define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248)
69 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
71 #define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C)
73 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
75 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
79 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
81 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
87 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
89 #define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250)
90 #define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254)
91 #define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258)
92 #define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C)
93 #define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260)
94 #define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264)
95 #define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270)
96 #define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274)
97 #define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C)
98 #define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284)
99 #define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C)
100 #define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294)
101 #define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C)
102 #define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304)
103 #define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C)
130 #define SPEAR1340_BUS_CLK_ENB 0
132 #define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310)
141 #define SPEAR1340_DDR_CTRL_CLK_ENB 0
143 #define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314)
166 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
167 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
168 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
170 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
171 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
173 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
178 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
179 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
180 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
181 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
189 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
190 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
191 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
192 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
193 {.div = 0x03031}, /* for vco1div2 = 250 MHz */
194 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
209 * 400 200 100 0x04000
210 * 400 250 125 0x03333
211 * 400 332 166 0x0268D
212 * 400 400 200 0x02000
214 * 500 200 100 0x05000
215 * 500 250 125 0x04000
216 * 500 332 166 0x03031
217 * 500 400 200 0x02800
218 * 500 500 250 0x02000
220 * 600 200 100 0x06000
221 * 600 250 125 0x04CCE
222 * 600 332 166 0x039D5
223 * 600 400 200 0x03000
224 * 600 500 250 0x02666
226 * 664 200 100 0x06a38
227 * 664 250 125 0x054FD
228 * 664 332 166 0x04000
229 * 664 400 200 0x0351E
230 * 664 500 250 0x02A7E
232 * 800 200 100 0x08000
233 * 800 250 125 0x06666
234 * 800 332 166 0x04D18
235 * 800 400 200 0x04000
236 * 800 500 250 0x03333
241 {.div = 0x08000},
242 {.div = 0x06a38},
243 {.div = 0x06666},
244 {.div = 0x06000},
245 {.div = 0x054FD},
246 {.div = 0x05000},
247 {.div = 0x04D18},
248 {.div = 0x04CCE},
249 {.div = 0x04000},
250 {.div = 0x039D5},
251 {.div = 0x0351E},
252 {.div = 0x03333},
253 {.div = 0x03031},
254 {.div = 0x03000},
255 {.div = 0x02A7E},
256 {.div = 0x02800},
257 {.div = 0x0268D},
258 {.div = 0x02666},
259 {.div = 0x02000},
265 {.xscale = 5, .yscale = 122, .eq = 0},
267 {.xscale = 10, .yscale = 204, .eq = 0},
269 {.xscale = 4, .yscale = 25, .eq = 0},
271 {.xscale = 4, .yscale = 21, .eq = 0},
273 {.xscale = 5, .yscale = 18, .eq = 0},
275 {.xscale = 2, .yscale = 6, .eq = 0},
277 {.xscale = 5, .yscale = 12, .eq = 0},
279 {.xscale = 2, .yscale = 4, .eq = 0},
293 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
294 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
301 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
302 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
303 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
304 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
305 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
306 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
307 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
308 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
309 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
310 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
311 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
312 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
313 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
314 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
315 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
316 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
317 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
318 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
319 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
320 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
351 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
352 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
353 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
354 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
360 {.xscale = 1, .yscale = 3, .eq = 0},
363 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
364 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
370 {.xscale = 1, .yscale = 4, .eq = 0},
371 {.xscale = 1, .yscale = 2, .eq = 0},
378 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
379 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
380 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
381 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
386 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
387 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
388 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
389 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
390 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
391 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
392 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
393 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
394 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
395 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
396 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
397 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
398 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
399 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
400 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
401 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
402 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
403 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
404 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
405 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
406 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
407 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
408 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
409 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
410 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
444 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1340_clk_init()
447 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1340_clk_init()
450 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1340_clk_init()
453 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1340_clk_init()
456 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1340_clk_init()
461 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, in spear1340_clk_init()
462 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0, in spear1340_clk_init()
471 SPEAR1340_PLL_CLK_MASK, 0, &_lock); in spear1340_clk_init()
473 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, in spear1340_clk_init()
482 SPEAR1340_PLL_CLK_MASK, 0, &_lock); in spear1340_clk_init()
484 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, in spear1340_clk_init()
493 SPEAR1340_PLL_CLK_MASK, 0, &_lock); in spear1340_clk_init()
495 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, in spear1340_clk_init()
502 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl, in spear1340_clk_init()
507 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, in spear1340_clk_init()
511 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, in spear1340_clk_init()
516 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, in spear1340_clk_init()
520 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, in spear1340_clk_init()
524 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, in spear1340_clk_init()
528 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, in spear1340_clk_init()
533 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, in spear1340_clk_init()
535 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, in spear1340_clk_init()
536 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0, in spear1340_clk_init()
541 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, in spear1340_clk_init()
546 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0, in spear1340_clk_init()
551 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0, in spear1340_clk_init()
559 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); in spear1340_clk_init()
562 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, in spear1340_clk_init()
566 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1, in spear1340_clk_init()
570 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, in spear1340_clk_init()
574 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, in spear1340_clk_init()
581 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock); in spear1340_clk_init()
584 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, in spear1340_clk_init()
592 SPEAR1340_GPT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
594 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, in spear1340_clk_init()
595 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0, in spear1340_clk_init()
602 SPEAR1340_GPT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
604 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, in spear1340_clk_init()
605 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0, in spear1340_clk_init()
612 SPEAR1340_GPT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
614 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, in spear1340_clk_init()
615 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0, in spear1340_clk_init()
622 SPEAR1340_GPT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
624 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, in spear1340_clk_init()
625 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0, in spear1340_clk_init()
631 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL, in spear1340_clk_init()
640 SPEAR1340_UART_CLK_MASK, 0, &_lock); in spear1340_clk_init()
645 SPEAR1340_UART0_CLK_ENB, 0, &_lock); in spear1340_clk_init()
649 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL, in spear1340_clk_init()
657 SPEAR1340_UART_CLK_MASK, 0, &_lock); in spear1340_clk_init()
660 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, in spear1340_clk_init()
661 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0, in spear1340_clk_init()
666 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL, in spear1340_clk_init()
673 SPEAR1340_SDHCI_CLK_ENB, 0, &_lock); in spear1340_clk_init()
677 0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl, in spear1340_clk_init()
684 SPEAR1340_CFXD_CLK_ENB, 0, &_lock); in spear1340_clk_init()
688 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, in spear1340_clk_init()
698 SPEAR1340_C3_CLK_MASK, 0, &_lock); in spear1340_clk_init()
702 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, in spear1340_clk_init()
711 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
715 0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl, in spear1340_clk_init()
723 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); in spear1340_clk_init()
724 clk_register_clkdev(clk, "stmmacphy.0", NULL); in spear1340_clk_init()
731 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
734 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, in spear1340_clk_init()
743 SPEAR1340_CLCD_CLK_MASK, 0, &_lock); in spear1340_clk_init()
746 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, in spear1340_clk_init()
747 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0, in spear1340_clk_init()
755 SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock); in spear1340_clk_init()
768 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock); in spear1340_clk_init()
771 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, in spear1340_clk_init()
773 0, &_lock); in spear1340_clk_init()
777 0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks, in spear1340_clk_init()
784 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, in spear1340_clk_init()
785 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0, in spear1340_clk_init()
789 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0, in spear1340_clk_init()
790 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0, in spear1340_clk_init()
794 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, in spear1340_clk_init()
795 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0, in spear1340_clk_init()
800 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, in spear1340_clk_init()
801 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0, in spear1340_clk_init()
805 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, in spear1340_clk_init()
806 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0, in spear1340_clk_init()
810 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, in spear1340_clk_init()
811 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0, in spear1340_clk_init()
815 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, in spear1340_clk_init()
816 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0, in spear1340_clk_init()
821 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, in spear1340_clk_init()
822 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0, in spear1340_clk_init()
827 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, in spear1340_clk_init()
828 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0, in spear1340_clk_init()
832 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, in spear1340_clk_init()
834 0, &_lock); in spear1340_clk_init()
838 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, in spear1340_clk_init()
839 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0, in spear1340_clk_init()
843 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, in spear1340_clk_init()
844 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0, in spear1340_clk_init()
849 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl, in spear1340_clk_init()
856 SPEAR1340_ADC_CLK_ENB, 0, &_lock); in spear1340_clk_init()
860 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0, in spear1340_clk_init()
861 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0, in spear1340_clk_init()
865 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, in spear1340_clk_init()
866 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0, in spear1340_clk_init()
870 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, in spear1340_clk_init()
871 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0, in spear1340_clk_init()
875 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0, in spear1340_clk_init()
876 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0, in spear1340_clk_init()
880 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0, in spear1340_clk_init()
881 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0, in spear1340_clk_init()
885 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, in spear1340_clk_init()
886 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0, in spear1340_clk_init()
895 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
902 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); in spear1340_clk_init()
905 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0, in spear1340_clk_init()
910 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0, in spear1340_clk_init()
915 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0, in spear1340_clk_init()
920 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0, in spear1340_clk_init()
927 SPEAR1340_MALI_CLK_ENB, 0, &_lock); in spear1340_clk_init()
930 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, in spear1340_clk_init()
931 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0, in spear1340_clk_init()
933 clk_register_clkdev(clk, NULL, "spear_cec.0"); in spear1340_clk_init()
935 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0, in spear1340_clk_init()
936 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0, in spear1340_clk_init()
944 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); in spear1340_clk_init()
949 SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock); in spear1340_clk_init()
956 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); in spear1340_clk_init()
961 SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock); in spear1340_clk_init()
964 clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0, in spear1340_clk_init()
965 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, in spear1340_clk_init()
969 clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0, in spear1340_clk_init()
970 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, in spear1340_clk_init()
974 clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0, in spear1340_clk_init()
976 0, &_lock); in spear1340_clk_init()
979 clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0, in spear1340_clk_init()
981 0, &_lock); in spear1340_clk_init()
984 clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0, in spear1340_clk_init()
985 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0, in spear1340_clk_init()
989 clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0, in spear1340_clk_init()
990 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, in spear1340_clk_init()
994 clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0, in spear1340_clk_init()
995 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, in spear1340_clk_init()
999 clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0, in spear1340_clk_init()
1000 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, in spear1340_clk_init()
1004 clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0, in spear1340_clk_init()
1005 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, in spear1340_clk_init()
1009 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0, in spear1340_clk_init()
1010 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0, in spear1340_clk_init()