Lines Matching +full:2 +full:c400000
24 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
26 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
28 #define SPEAR1310_PLL_CLK_MASK 2
52 #define SPEAR1310_UART_CLK_SYNT_VAL 2
53 #define SPEAR1310_UART_CLK_MASK 2
58 #define SPEAR1310_CLCD_CLK_MASK 2
59 #define SPEAR1310_CLCD_CLK_SHIFT 2
68 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
85 #define SPEAR1310_I2S_REF_SHIFT 2
86 #define SPEAR1310_I2S_SRC_CLK_MASK 2
132 #define SPEAR1310_SYSRAM1_CLK_ENB 2
144 #define SPEAR1310_CPU_DBG_CLK_ENB 2
165 #define SPEAR1310_OSC_24M_CLK_ENB 2
198 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
224 #define SPEAR1310_MII1_CLK_ENB 2
255 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
256 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
258 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
264 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
265 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
267 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
326 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
333 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
341 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
460 2); in spear1310_clk_init()
468 2); in spear1310_clk_init()
472 2); in spear1310_clk_init()
490 CLK_SET_RATE_PARENT, 1, 2); in spear1310_clk_init()
494 2); in spear1310_clk_init()
498 2); in spear1310_clk_init()
912 clk_register_clkdev(clk, NULL, "5c400000.eth"); in spear1310_clk_init()
936 clk_register_clkdev(clk, "stmmacphy.2", NULL); in spear1310_clk_init()