Lines Matching +full:i2c +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/s3c2410.h>
16 #include "clk-pll.h"
78 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
79 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
80 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
81 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
82 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
83 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
84 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
85 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
86 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
87 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
88 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
89 GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
90 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
91 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
92 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
95 /* should be added _after_ the soc-specific clocks are created */
97 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
102 ALIAS(HCLK_USBD, NULL, "usb-device"),
103 ALIAS(HCLK_USBH, NULL, "usb-host"),
104 ALIAS(UCLK, NULL, "usb-bus-host"),
105 ALIAS(UCLK, NULL, "usb-bus-gadget"),
115 ALIAS(PCLK_I2C, NULL, "i2c"),
177 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
178 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
179 ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
180 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
181 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
182 ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
261 GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
265 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
266 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
267 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
268 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
269 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
270 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
272 ALIAS(CAMIF, NULL, "camif-upll"),
284 GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
301 * Only necessary until the devicetree-move is complete
336 hws = ctx->clk_data.hws; in s3c2410_common_clk_init()
338 /* Register external clocks only in non-dt cases */ in s3c2410_common_clk_init()
388 /* Register SoC-specific clocks. */ in s3c2410_common_clk_init()
434 CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
440 CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
446 CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);