Lines Matching full:fin_pll
167 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
169 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
171 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
173 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
178 PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
179 PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
180 PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
181 PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
182 PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
183 PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
184 PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
186 PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
187 PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
188 PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" };
491 PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" };
492 PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
493 PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
494 PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" };
495 PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" };
496 PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
497 PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" };
498 PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
528 "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
529 GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
531 GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll",
535 GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
537 GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
800 PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" };
801 PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" };
802 PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" };
831 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll",
882 GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll",
911 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll",
957 "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
1048 PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" };
1049 PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" };
1097 GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll",
1120 GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll",
1122 GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll",
1272 PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };
1273 PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };
1274 PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };
1285 DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
1291 GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
1293 GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
1295 GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
1297 GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
1299 GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
1301 GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
1303 GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
1305 GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
1307 GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
1385 GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
1395 GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
1482 PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
1486 PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" };
1487 PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" };
1488 PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" };
1642 PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
1646 PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };