Lines Matching +full:0 +full:x209c
22 /* Register Offset definitions for CMU_TOP (0x120e0000) */
23 #define PLL_LOCKTIME_PLL_MMC 0x0000
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
25 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
26 #define PLL_CON0_PLL_MMC 0x0100
27 #define PLL_CON3_PLL_MMC 0x010c
28 #define PLL_CON0_PLL_SHARED0 0x0140
29 #define PLL_CON3_PLL_SHARED0 0x014c
30 #define PLL_CON0_PLL_SHARED1 0x0180
31 #define PLL_CON3_PLL_SHARED1 0x018c
32 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
33 #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
34 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
35 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
36 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
37 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
38 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
39 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
40 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
41 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
42 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
43 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
44 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
45 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
46 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
47 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
48 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
49 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
50 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
51 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
52 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
53 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
54 #define CLK_CON_DIV_CLKCMU_AUD 0x1810
55 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
56 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
57 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
58 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
59 #define CLK_CON_DIV_CLKCMU_DPU 0x1840
60 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
61 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
62 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
63 #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
64 #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
65 #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
66 #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
67 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
68 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
69 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
70 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
71 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
72 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
73 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
74 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
75 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
76 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
77 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
78 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
79 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
80 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
81 #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
82 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
83 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
84 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
85 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
86 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
87 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
88 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
89 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
90 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
91 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
92 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
93 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
94 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
95 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
96 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
97 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
98 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
99 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
100 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
266 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
270 CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
274 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
276 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
278 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
280 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
284 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
288 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
290 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
292 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
296 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
298 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
300 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
302 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
306 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
308 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
310 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
312 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
316 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
318 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
320 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
326 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
328 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
330 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
332 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
334 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
336 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
340 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
344 CLK_CON_DIV_CLKCMU_AUD, 0, 4),
348 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
350 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
352 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
354 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
358 CLK_CON_DIV_CLKCMU_DPU, 0, 4),
362 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
364 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
366 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
370 CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
372 CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
374 CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
376 CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
380 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
382 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
384 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
386 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
390 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
392 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
394 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
400 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
402 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
404 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
406 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
410 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
414 CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
418 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
422 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
424 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
426 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
431 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
433 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
435 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
437 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
442 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
444 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
446 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
448 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
452 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
454 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
456 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
484 /* Register Offset definitions for CMU_APM (0x11800000) */
485 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
486 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
487 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
488 #define PLL_CON0_MUX_DLL_USER 0x0630
489 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
490 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
491 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
492 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
493 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
494 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
495 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
496 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
497 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
498 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
499 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
500 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
501 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
502 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
503 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
504 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
540 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
541 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
542 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
543 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
556 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
558 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
560 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
566 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
568 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
570 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
575 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
578 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
580 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
582 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
584 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
586 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
588 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
592 0),
594 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
596 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
616 #define PLL_LOCKTIME_PLL_AUD 0x0000
617 #define PLL_CON0_PLL_AUD 0x0100
618 #define PLL_CON3_PLL_AUD 0x010c
619 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
620 #define PLL_CON0_MUX_TICK_USB_USER 0x0610
621 #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
622 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
623 #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
624 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
625 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
626 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
627 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
628 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
629 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
630 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
631 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
632 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
633 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
634 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
635 #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
636 #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
637 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
638 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
639 #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
640 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
641 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
642 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
643 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
644 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
645 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
646 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
647 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
648 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
649 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
650 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
651 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
652 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
653 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
654 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
655 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
656 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
657 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
658 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
659 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
660 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
661 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
662 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
663 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
664 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
665 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
666 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
667 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
668 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
751 FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
752 FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
753 FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
754 FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
755 FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
756 FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
757 FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
758 FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
770 CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
772 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
774 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
776 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
778 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
780 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
782 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
784 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
786 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
788 CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
793 CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
795 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
797 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
799 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
801 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
804 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
806 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
808 CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
810 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
812 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
814 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
816 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
818 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
820 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
822 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
824 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
826 CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
831 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
833 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
835 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
838 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
840 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
842 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
844 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
846 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
848 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
850 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
852 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
854 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
856 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
858 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
860 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
862 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
864 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
866 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
868 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
870 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
872 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
894 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
895 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
896 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
897 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
898 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
899 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
900 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
901 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
902 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
903 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
904 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
905 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
906 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
907 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
908 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
933 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
938 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
940 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
942 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
947 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
949 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
951 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
957 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
960 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
964 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
966 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
969 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
971 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
974 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
977 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
997 /* Register Offset definitions for CMU_HSI (0x13400000) */
998 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
999 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
1000 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
1001 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
1002 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
1003 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
1004 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
1005 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
1006 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
1007 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
1008 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
1009 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
1010 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
1039 4, 1, CLK_SET_RATE_PARENT, 0),
1044 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
1049 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
1051 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
1053 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
1056 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1058 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
1061 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
1064 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
1066 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
1069 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
1085 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
1086 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
1087 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
1088 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
1089 #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
1090 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
1091 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
1092 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
1093 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
1094 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
1095 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
1096 #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
1097 #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
1098 #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
1099 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
1100 #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
1101 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
1102 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
1103 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
1104 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
1105 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
1106 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
1107 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
1154 CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1160 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1162 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1164 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1166 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1168 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1171 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1173 CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1175 CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1177 CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1179 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1181 CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1184 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1186 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1189 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1191 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1194 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1197 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1199 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1217 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
1218 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
1219 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
1220 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
1221 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
1222 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
1223 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
1224 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
1225 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
1226 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
1227 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
1228 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
1229 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
1230 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
1231 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
1274 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1281 21, CLK_IGNORE_UNUSED, 0),
1284 21, 0, 0),
1287 21, 0, 0),
1290 21, 0, 0),
1293 21, 0, 0),
1296 21, 0, 0),
1299 21, 0, 0),
1302 21, 0, 0),
1305 21, 0, 0),
1308 21, 0, 0),
1326 /* Register Offset definitions for CMU_PERI (0x10030000) */
1327 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
1328 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
1329 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
1330 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
1331 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
1332 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
1333 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
1334 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
1335 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
1336 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
1337 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
1338 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
1339 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
1340 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
1341 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
1342 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
1343 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
1344 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
1345 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
1346 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
1347 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
1348 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
1349 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
1350 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
1351 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
1352 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
1353 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
1354 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
1355 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
1356 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
1357 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
1358 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
1359 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
1360 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
1418 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
1420 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
1422 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
1424 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
1429 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
1431 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
1433 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
1435 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
1437 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
1439 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
1441 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
1443 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
1445 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
1447 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
1449 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
1451 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
1453 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
1455 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
1457 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
1459 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
1461 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
1464 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
1466 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
1468 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
1471 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
1473 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
1475 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
1477 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
1479 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
1483 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1510 /* Register Offset definitions for CMU_CORE (0x12000000) */
1511 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1512 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
1513 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
1514 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
1515 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
1516 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1517 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
1518 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
1519 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
1520 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
1521 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
1522 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
1523 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
1524 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
1557 4, 1, CLK_SET_RATE_PARENT, 0),
1561 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
1566 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
1572 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
1575 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
1577 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
1580 21, CLK_SET_RATE_PARENT, 0),
1582 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
1584 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
1587 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1590 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
1608 /* Register Offset definitions for CMU_DPU (0x13000000) */
1609 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
1610 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
1611 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
1612 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
1613 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
1614 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
1615 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
1616 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
1617 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
1618 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
1643 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
1650 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1652 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
1654 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
1656 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
1658 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
1660 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
1662 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
1664 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
1690 return 0; in exynos850_cmu_probe()