Lines Matching +full:0 +full:x105e0000
13 /* Register Offset definitions for CMU_TOPC (0x10570000) */
14 #define CC_PLL_LOCK 0x0000
15 #define BUS0_PLL_LOCK 0x0004
16 #define BUS1_DPLL_LOCK 0x0008
17 #define MFC_PLL_LOCK 0x000C
18 #define AUD_PLL_LOCK 0x0010
19 #define CC_PLL_CON0 0x0100
20 #define BUS0_PLL_CON0 0x0110
21 #define BUS1_DPLL_CON0 0x0120
22 #define MFC_PLL_CON0 0x0130
23 #define AUD_PLL_CON0 0x0140
24 #define MUX_SEL_TOPC0 0x0200
25 #define MUX_SEL_TOPC1 0x0204
26 #define MUX_SEL_TOPC2 0x0208
27 #define MUX_SEL_TOPC3 0x020C
28 #define DIV_TOPC0 0x0600
29 #define DIV_TOPC1 0x0604
30 #define DIV_TOPC3 0x060C
31 #define ENABLE_ACLK_TOPC0 0x0800
32 #define ENABLE_ACLK_TOPC1 0x0804
33 #define ENABLE_SCLK_TOPC1 0x0A04
36 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
37 FFACTOR(0, "ffac_topc_bus0_pll_div4",
38 "ffac_topc_bus0_pll_div2", 1, 2, 0),
39 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
40 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
41 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
89 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
90 MUX_SEL_TOPC0, 0, 1),
91 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
93 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
95 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
97 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
99 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
101 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
103 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
106 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
107 MUX_SEL_TOPC1, 0, 1),
108 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
111 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
113 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
114 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
127 DIV_TOPC3, 0, 4),
139 PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
145 ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
148 ENABLE_ACLK_TOPC1, 20, 0, 0),
151 ENABLE_ACLK_TOPC1, 24, 0, 0),
154 ENABLE_SCLK_TOPC1, 20, 0, 0),
156 ENABLE_SCLK_TOPC1, 17, 0, 0),
158 ENABLE_SCLK_TOPC1, 16, 0, 0),
160 ENABLE_SCLK_TOPC1, 13, 0, 0),
162 ENABLE_SCLK_TOPC1, 12, 0, 0),
164 ENABLE_SCLK_TOPC1, 5, 0, 0),
166 ENABLE_SCLK_TOPC1, 4, 0, 0),
168 ENABLE_SCLK_TOPC1, 1, 0, 0),
170 ENABLE_SCLK_TOPC1, 0, 0, 0),
174 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
176 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
178 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
180 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
210 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */
211 #define MUX_SEL_TOP00 0x0200
212 #define MUX_SEL_TOP01 0x0204
213 #define MUX_SEL_TOP03 0x020C
214 #define MUX_SEL_TOP0_PERIC0 0x0230
215 #define MUX_SEL_TOP0_PERIC1 0x0234
216 #define MUX_SEL_TOP0_PERIC2 0x0238
217 #define MUX_SEL_TOP0_PERIC3 0x023C
218 #define DIV_TOP03 0x060C
219 #define DIV_TOP0_PERIC0 0x0630
220 #define DIV_TOP0_PERIC1 0x0634
221 #define DIV_TOP0_PERIC2 0x0638
222 #define DIV_TOP0_PERIC3 0x063C
223 #define ENABLE_ACLK_TOP03 0x080C
224 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30
225 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34
226 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38
227 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
275 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
276 MUX_SEL_TOP00, 0, 1),
277 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
279 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
281 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
283 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
286 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
288 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
290 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
292 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
295 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
296 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
298 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
299 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
300 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
302 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
303 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
305 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
306 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
307 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
308 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
309 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
310 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
311 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
320 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
321 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
322 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
324 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
325 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
327 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
328 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
330 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
331 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
332 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
333 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
334 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
339 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
341 ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
344 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
346 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
348 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
351 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
353 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
356 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
358 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
360 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
362 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
364 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
366 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
368 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
372 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
373 1, 2, 0),
374 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
375 1, 2, 0),
376 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
377 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
402 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */
403 #define MUX_SEL_TOP10 0x0200
404 #define MUX_SEL_TOP11 0x0204
405 #define MUX_SEL_TOP13 0x020C
406 #define MUX_SEL_TOP1_FSYS0 0x0224
407 #define MUX_SEL_TOP1_FSYS1 0x0228
408 #define MUX_SEL_TOP1_FSYS11 0x022C
409 #define DIV_TOP13 0x060C
410 #define DIV_TOP1_FSYS0 0x0624
411 #define DIV_TOP1_FSYS1 0x0628
412 #define DIV_TOP1_FSYS11 0x062C
413 #define ENABLE_ACLK_TOP13 0x080C
414 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24
415 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28
416 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
455 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
457 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
459 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
461 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
464 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
466 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
468 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
470 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
473 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
474 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
476 MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
477 MUX_SEL_TOP1_FSYS0, 0, 2),
478 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
479 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
482 MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
483 MUX_SEL_TOP1_FSYS1, 0, 2),
484 MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
487 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
488 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
489 MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
500 "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
508 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
512 DIV_TOP1_FSYS11, 0, 10),
522 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
523 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
524 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
527 ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
530 ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
533 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
535 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
539 CLK_IS_CRITICAL, 0),
546 CLK_IS_CRITICAL, 0),
550 24, CLK_SET_RATE_PARENT, 0),
554 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
555 1, 2, 0),
556 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
557 1, 2, 0),
558 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
559 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
584 /* Register Offset definitions for CMU_CCORE (0x105B0000) */
585 #define MUX_SEL_CCORE 0x0200
586 #define DIV_CCORE 0x0600
587 #define ENABLE_ACLK_CCORE0 0x0800
588 #define ENABLE_ACLK_CCORE1 0x0804
589 #define ENABLE_PCLK_CCORE 0x0900
602 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
608 ENABLE_PCLK_CCORE, 8, 0, 0),
629 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
630 #define MUX_SEL_PERIC0 0x0200
631 #define ENABLE_PCLK_PERIC0 0x0900
632 #define ENABLE_SCLK_PERIC0 0x0A00
645 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
646 MUX_SEL_PERIC0, 0, 1),
647 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
653 ENABLE_PCLK_PERIC0, 8, 0, 0),
655 ENABLE_PCLK_PERIC0, 9, 0, 0),
657 ENABLE_PCLK_PERIC0, 10, 0, 0),
659 ENABLE_PCLK_PERIC0, 11, 0, 0),
661 ENABLE_PCLK_PERIC0, 12, 0, 0),
663 ENABLE_PCLK_PERIC0, 13, 0, 0),
665 ENABLE_PCLK_PERIC0, 14, 0, 0),
667 ENABLE_PCLK_PERIC0, 16, 0, 0),
669 ENABLE_PCLK_PERIC0, 20, 0, 0),
671 ENABLE_PCLK_PERIC0, 21, 0, 0),
674 ENABLE_SCLK_PERIC0, 16, 0, 0),
675 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
693 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
694 #define MUX_SEL_PERIC10 0x0200
695 #define MUX_SEL_PERIC11 0x0204
696 #define MUX_SEL_PERIC12 0x0208
697 #define ENABLE_PCLK_PERIC1 0x0900
698 #define ENABLE_SCLK_PERIC10 0x0A00
723 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
724 MUX_SEL_PERIC10, 0, 1),
726 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
727 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
728 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
729 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
730 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
731 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
732 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
733 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
734 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
735 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
736 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
738 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
740 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
746 ENABLE_PCLK_PERIC1, 4, 0, 0),
748 ENABLE_PCLK_PERIC1, 5, 0, 0),
750 ENABLE_PCLK_PERIC1, 6, 0, 0),
752 ENABLE_PCLK_PERIC1, 7, 0, 0),
754 ENABLE_PCLK_PERIC1, 8, 0, 0),
756 ENABLE_PCLK_PERIC1, 9, 0, 0),
758 ENABLE_PCLK_PERIC1, 10, 0, 0),
760 ENABLE_PCLK_PERIC1, 11, 0, 0),
762 ENABLE_PCLK_PERIC1, 12, 0, 0),
764 ENABLE_PCLK_PERIC1, 13, 0, 0),
766 ENABLE_PCLK_PERIC1, 14, 0, 0),
768 ENABLE_PCLK_PERIC1, 15, 0, 0),
770 ENABLE_PCLK_PERIC1, 16, 0, 0),
772 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
774 ENABLE_PCLK_PERIC1, 18, 0, 0),
776 ENABLE_PCLK_PERIC1, 19, 0, 0),
779 ENABLE_SCLK_PERIC10, 9, 0, 0),
781 ENABLE_SCLK_PERIC10, 10, 0, 0),
783 ENABLE_SCLK_PERIC10, 11, 0, 0),
785 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
787 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
789 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
791 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
793 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
795 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
797 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
799 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
820 /* Register Offset definitions for CMU_PERIS (0x10040000) */
821 #define MUX_SEL_PERIS 0x0200
822 #define ENABLE_PCLK_PERIS 0x0900
823 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
824 #define ENABLE_SCLK_PERIS 0x0A00
825 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
839 MUX(0, "mout_aclk_peris_66_user",
840 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
845 ENABLE_PCLK_PERIS, 6, 0, 0),
847 ENABLE_PCLK_PERIS, 10, 0, 0),
850 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
852 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
854 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
875 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
876 #define MUX_SEL_FSYS00 0x0200
877 #define MUX_SEL_FSYS01 0x0204
878 #define MUX_SEL_FSYS02 0x0208
879 #define ENABLE_ACLK_FSYS00 0x0800
880 #define ENABLE_ACLK_FSYS01 0x0804
881 #define ENABLE_SCLK_FSYS01 0x0A04
882 #define ENABLE_SCLK_FSYS02 0x0A08
883 #define ENABLE_SCLK_FSYS04 0x0A10
899 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
900 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
915 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
918 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
920 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
923 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
926 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
933 ENABLE_ACLK_FSYS00, 3, 0, 0),
935 ENABLE_ACLK_FSYS00, 4, 0, 0),
938 ENABLE_ACLK_FSYS00, 19, 0, 0),
941 ENABLE_ACLK_FSYS01, 29, 0, 0),
943 ENABLE_ACLK_FSYS01, 31, 0, 0),
947 ENABLE_SCLK_FSYS01, 4, 0, 0),
949 ENABLE_SCLK_FSYS01, 8, 0, 0),
954 ENABLE_SCLK_FSYS02, 24, 0, 0),
958 ENABLE_SCLK_FSYS02, 28, 0, 0),
962 ENABLE_SCLK_FSYS04, 28, 0, 0),
985 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
986 #define MUX_SEL_FSYS10 0x0200
987 #define MUX_SEL_FSYS11 0x0204
988 #define MUX_SEL_FSYS12 0x0208
989 #define DIV_FSYS1 0x0600
990 #define ENABLE_ACLK_FSYS1 0x0800
991 #define ENABLE_PCLK_FSYS1 0x0900
992 #define ENABLE_SCLK_FSYS11 0x0A04
993 #define ENABLE_SCLK_FSYS12 0x0A08
994 #define ENABLE_SCLK_FSYS13 0x0A0C
1012 0, 300000000),
1014 0, 300000000),
1016 0, 300000000),
1034 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
1036 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
1039 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
1041 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
1043 MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
1046 MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
1048 MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
1050 MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
1056 DIV_FSYS1, 0, 2),
1062 ENABLE_SCLK_FSYS11, 20, 0, 0),
1065 ENABLE_ACLK_FSYS1, 29, 0, 0),
1067 ENABLE_ACLK_FSYS1, 30, 0, 0),
1070 ENABLE_ACLK_FSYS1, 31, 0, 0),
1072 ENABLE_PCLK_FSYS1, 30, 0, 0),
1076 ENABLE_SCLK_FSYS12, 16, 0, 0),
1079 ENABLE_SCLK_FSYS12, 24, 0, 0),
1082 ENABLE_SCLK_FSYS12, 28, 0, 0),
1087 ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
1091 ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
1116 #define MUX_SEL_MSCL 0x0200
1117 #define DIV_MSCL 0x0600
1118 #define ENABLE_ACLK_MSCL 0x0800
1119 #define ENABLE_PCLK_MSCL 0x0900
1133 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
1137 DIV_MSCL, 0, 3),
1142 ENABLE_ACLK_MSCL, 31, 0, 0),
1144 ENABLE_ACLK_MSCL, 30, 0, 0),
1146 ENABLE_ACLK_MSCL, 29, 0, 0),
1148 ENABLE_ACLK_MSCL, 28, 0, 0),
1151 ENABLE_ACLK_MSCL, 27, 0, 0),
1154 ENABLE_ACLK_MSCL, 26, 0, 0),
1156 ENABLE_ACLK_MSCL, 25, 0, 0),
1158 ENABLE_ACLK_MSCL, 24, 0, 0),
1161 ENABLE_ACLK_MSCL, 23, 0, 0),
1163 ENABLE_ACLK_MSCL, 22, 0, 0),
1165 ENABLE_ACLK_MSCL, 21, 0, 0),
1167 ENABLE_ACLK_MSCL, 20, 0, 0),
1169 ENABLE_ACLK_MSCL, 19, 0, 0),
1171 ENABLE_ACLK_MSCL, 18, 0, 0),
1173 ENABLE_ACLK_MSCL, 17, 0, 0),
1175 ENABLE_ACLK_MSCL, 16, 0, 0),
1178 ENABLE_ACLK_MSCL, 15, 0, 0),
1181 ENABLE_ACLK_MSCL, 14, 0, 0),
1184 ENABLE_PCLK_MSCL, 31, 0, 0),
1186 ENABLE_PCLK_MSCL, 30, 0, 0),
1188 ENABLE_PCLK_MSCL, 29, 0, 0),
1190 ENABLE_PCLK_MSCL, 28, 0, 0),
1192 ENABLE_PCLK_MSCL, 27, 0, 0),
1194 ENABLE_PCLK_MSCL, 26, 0, 0),
1196 ENABLE_PCLK_MSCL, 25, 0, 0),
1198 ENABLE_PCLK_MSCL, 24, 0, 0),
1200 ENABLE_PCLK_MSCL, 23, 0, 0),
1202 ENABLE_PCLK_MSCL, 22, 0, 0),
1204 ENABLE_PCLK_MSCL, 21, 0, 0),
1206 ENABLE_PCLK_MSCL, 20, 0, 0),
1229 /* Register Offset definitions for CMU_AUD (0x114C0000) */
1230 #define MUX_SEL_AUD 0x0200
1231 #define DIV_AUD0 0x0600
1232 #define DIV_AUD1 0x0604
1233 #define ENABLE_ACLK_AUD 0x0800
1234 #define ENABLE_PCLK_AUD 0x0900
1235 #define ENABLE_SCLK_AUD 0x0A00
1253 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1254 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1255 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1259 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1260 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1261 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1263 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1264 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1265 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1266 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1267 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1272 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1274 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1275 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1276 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1277 ENABLE_SCLK_AUD, 30, 0, 0),
1279 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1280 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1281 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1282 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1283 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1284 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1286 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1288 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1289 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1290 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1292 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1293 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1294 ENABLE_ACLK_AUD, 28, 0, 0),
1295 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),