Lines Matching refs:ENABLE_PCLK_AUD
2911 #define ENABLE_PCLK_AUD 0x0900 macro
2925 ENABLE_PCLK_AUD,
2999 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
3001 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3003 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3006 ENABLE_PCLK_AUD, 10, 0, 0),
3008 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3010 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3012 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3014 ENABLE_PCLK_AUD, 6, 0, 0),
3016 ENABLE_PCLK_AUD, 5, 0, 0),
3018 ENABLE_PCLK_AUD, 4, 0, 0),
3020 ENABLE_PCLK_AUD, 3, 0, 0),
3021 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3024 ENABLE_PCLK_AUD, 0, 0, 0),