1 // SPDX-License-Identifier: GPL-2.0
5 // Common Clock Framework support for Exynos5 power-domain dependent clocks
14 #include "clk-exynos5-subcmu.h"
24 	for (; num_regs > 0; --num_regs, ++rd) {  in exynos5_subcmu_clk_save()
25 		rd->save = readl(base + rd->offset);  in exynos5_subcmu_clk_save()
26 		writel((rd->save & ~rd->mask) | rd->value, base + rd->offset);  in exynos5_subcmu_clk_save()
27 		rd->save &= rd->mask;  in exynos5_subcmu_clk_save()
35 	for (; num_regs > 0; --num_regs, ++rd)  in exynos5_subcmu_clk_restore()
36 		writel((readl(base + rd->offset) & ~rd->mask) | rd->save,  in exynos5_subcmu_clk_restore()
37 		       base + rd->offset);  in exynos5_subcmu_clk_restore()
43 	while (nr_clk--)  in exynos5_subcmu_defer_gate()
44 		samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id);  in exynos5_subcmu_defer_gate()
48  * Pass the needed clock provider context and register sub-CMU clocks
50  * NOTE: This function has to be called from the main, OF_CLK_DECLARE-
53  * drivers: one which binds to the same device-tree node as OF_CLK_DECLARE
54  * driver and second, for handling its per-domain child-devices. Those
56  * when OF-core populates all device-tree nodes.
65 	for (; _nr_cmus--; _cmu++) {  in exynos5_subcmus_init()
66 		exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,  in exynos5_subcmus_init()
67 					  (*_cmu)->nr_gate_clks);  in exynos5_subcmus_init()
68 		exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,  in exynos5_subcmus_init()
69 					(*_cmu)->nr_suspend_regs);  in exynos5_subcmus_init()
78 	spin_lock_irqsave(&ctx->lock, flags);  in exynos5_subcmu_suspend()
79 	exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs,  in exynos5_subcmu_suspend()
80 				info->nr_suspend_regs);  in exynos5_subcmu_suspend()
81 	spin_unlock_irqrestore(&ctx->lock, flags);  in exynos5_subcmu_suspend()
91 	spin_lock_irqsave(&ctx->lock, flags);  in exynos5_subcmu_resume()
92 	exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs,  in exynos5_subcmu_resume()
93 				   info->nr_suspend_regs);  in exynos5_subcmu_resume()
94 	spin_unlock_irqrestore(&ctx->lock, flags);  in exynos5_subcmu_resume()
101 	struct device *dev = &pdev->dev;  in exynos5_subcmu_probe()
108 	ctx->dev = dev;  in exynos5_subcmu_probe()
109 	samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks);  in exynos5_subcmu_probe()
110 	samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks);  in exynos5_subcmu_probe()
111 	ctx->dev = NULL;  in exynos5_subcmu_probe()
127 		.name = "exynos5-subcmu",
142 	pdev = platform_device_alloc("exynos5-subcmu", PLATFORM_DEVID_AUTO);  in exynos5_clk_register_subcmu()
144 		return -ENOMEM;  in exynos5_clk_register_subcmu()
146 	pdev->dev.parent = parent;  in exynos5_clk_register_subcmu()
148 	of_genpd_add_device(&genpdspec, &pdev->dev);  in exynos5_clk_register_subcmu()
162 	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {  in exynos5_clk_probe()
166 			if (strcmp(cmu[i]->pd_name, name) == 0)  in exynos5_clk_probe()
167 				exynos5_clk_register_subcmu(&pdev->dev,  in exynos5_clk_probe()
174 	{ .compatible = "samsung,exynos5250-clock", },
175 	{ .compatible = "samsung,exynos5420-clock", },
176 	{ .compatible = "samsung,exynos5800-clock", },
182 		.name = "exynos5-clock",