Lines Matching full:fin_pll
279 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
280 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
281 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
282 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
283 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
335 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
353 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
354 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
355 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
1010 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1012 * mapped space. So to determine the parent of fin_pll clock, the chipid
1048 "fin_pll clock frequency is 24MHz\n", __func__, in exynos4_clk_register_finpll()
1055 fclk.name = "fin_pll"; in exynos4_clk_register_finpll()
1147 [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1149 [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1151 [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1158 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1160 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1162 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1164 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",