Lines Matching +full:5 +full:mhz
131 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
446 CLKOUT_CMU_LEFTBUS, 0, 5),
450 CLKOUT_CMU_RIGHTBUS, 0, 5),
497 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
500 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
502 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
510 CLKOUT_CMU_LEFTBUS, 0, 5),
515 CLKOUT_CMU_RIGHTBUS, 0, 5),
519 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
578 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
585 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
739 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
805 GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
822 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
834 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
839 GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
919 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
923 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
966 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
1048 "fin_pll clock frequency is 24MHz\n", __func__, in exynos4_clk_register_finpll()
1071 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1072 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1073 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1074 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1075 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1076 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1077 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1078 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1079 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1084 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
1085 PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
1086 PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
1087 PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1),
1088 PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1),
1089 PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
1090 PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
1095 PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
1096 PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1),
1097 PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
1098 PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
1099 PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
1104 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1105 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1106 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1107 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1108 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1109 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1110 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1111 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1112 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1113 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
1114 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
1115 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
1116 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
1117 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
1118 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
1119 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
1124 PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
1125 PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
1126 PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
1127 PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
1128 PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710),
1129 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762),
1130 PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961),
1131 PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381),
1136 PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
1137 PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
1138 PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
1139 PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
1140 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
1141 PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024),
1142 PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024),
1199 { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
1216 { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
1217 { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
1218 { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
1219 { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
1220 { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
1221 { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },