59 	const struct rockchip_cpuclk_reg_data	*reg_data;  member
86 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;  in rockchip_cpuclk_recalc_rate()  local
87 	u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);  in rockchip_cpuclk_recalc_rate()
89 	clksel0 >>= reg_data->div_core_shift[0];  in rockchip_cpuclk_recalc_rate()
90 	clksel0 &= reg_data->div_core_mask[0];  in rockchip_cpuclk_recalc_rate()
119 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;  in rockchip_cpuclk_pre_rate_change()  local
146 		if (alt_div > reg_data->div_core_mask[0]) {  in rockchip_cpuclk_pre_rate_change()
148 				__func__, alt_div, reg_data->div_core_mask[0]);  in rockchip_cpuclk_pre_rate_change()
149 			alt_div = reg_data->div_core_mask[0];  in rockchip_cpuclk_pre_rate_change()
162 		for (i = 0; i < reg_data->num_cores; i++) {  in rockchip_cpuclk_pre_rate_change()
163 			writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],  in rockchip_cpuclk_pre_rate_change()
164 					     reg_data->div_core_shift[i]),  in rockchip_cpuclk_pre_rate_change()
165 			       cpuclk->reg_base + reg_data->core_reg[i]);  in rockchip_cpuclk_pre_rate_change()
169 	writel(HIWORD_UPDATE(reg_data->mux_core_alt,  in rockchip_cpuclk_pre_rate_change()
170 			     reg_data->mux_core_mask,  in rockchip_cpuclk_pre_rate_change()
171 			     reg_data->mux_core_shift),  in rockchip_cpuclk_pre_rate_change()
172 	       cpuclk->reg_base + reg_data->core_reg[0]);  in rockchip_cpuclk_pre_rate_change()
181 	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;  in rockchip_cpuclk_post_rate_change()  local
205 	writel(HIWORD_UPDATE(reg_data->mux_core_main,  in rockchip_cpuclk_post_rate_change()
206 			     reg_data->mux_core_mask,  in rockchip_cpuclk_post_rate_change()
207 			     reg_data->mux_core_shift),  in rockchip_cpuclk_post_rate_change()
208 	       cpuclk->reg_base + reg_data->core_reg[0]);  in rockchip_cpuclk_post_rate_change()
211 	for (i = 0; i < reg_data->num_cores; i++) {  in rockchip_cpuclk_post_rate_change()
212 		writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],  in rockchip_cpuclk_post_rate_change()
213 				     reg_data->div_core_shift[i]),  in rockchip_cpuclk_post_rate_change()
214 		       cpuclk->reg_base + reg_data->core_reg[i]);  in rockchip_cpuclk_post_rate_change()
249 			const struct rockchip_cpuclk_reg_data *reg_data,  in rockchip_clk_register_cpuclk()  argument
268 	init.parent_names = &parent_names[reg_data->mux_core_main];  in rockchip_clk_register_cpuclk()
282 	cpuclk->reg_data = reg_data;  in rockchip_clk_register_cpuclk()
286 	cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);  in rockchip_clk_register_cpuclk()
289 		       __func__, reg_data->mux_core_alt);  in rockchip_clk_register_cpuclk()
301 	clk = __clk_lookup(parent_names[reg_data->mux_core_main]);  in rockchip_clk_register_cpuclk()
304 		       __func__, reg_data->mux_core_main,  in rockchip_clk_register_cpuclk()
305 		       parent_names[reg_data->mux_core_main]);  in rockchip_clk_register_cpuclk()