Lines Matching +full:0 +full:x414
12 #define CPG_SIPLL5_STBY (0x140)
13 #define CPG_SIPLL5_CLK1 (0x144)
14 #define CPG_SIPLL5_CLK3 (0x14C)
15 #define CPG_SIPLL5_CLK4 (0x150)
16 #define CPG_SIPLL5_CLK5 (0x154)
17 #define CPG_SIPLL5_MON (0x15C)
18 #define CPG_PL1_DDIV (0x200)
19 #define CPG_PL2_DDIV (0x204)
20 #define CPG_PL3A_DDIV (0x208)
21 #define CPG_PL6_DDIV (0x210)
22 #define CPG_PL2SDHI_DSEL (0x218)
23 #define CPG_CLKSTATUS (0x280)
24 #define CPG_PL3_SSEL (0x408)
25 #define CPG_PL6_SSEL (0x414)
26 #define CPG_PL6_ETH_SSEL (0x418)
27 #define CPG_PL5_SDIV (0x420)
28 #define CPG_RST_MON (0x680)
29 #define CPG_OTHERFUNC1_REG (0xBE8)
31 #define CPG_SIPLL5_STBY_RESETB BIT(0)
38 #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF)
51 /* n = 0/1/2 for PLL1/4/6 */
52 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n))
53 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n))
59 #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)
60 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
62 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
65 #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)
71 #define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)
72 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
75 #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)