190 	struct sd_hw_data *hwdata = to_sd_hw_data(hw);  in rzg2l_cpg_sd_clk_mux_set_parent()  local
191 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_sd_clk_mux_set_parent()
192 	u32 off = GET_REG_OFFSET(hwdata->conf);  in rzg2l_cpg_sd_clk_mux_set_parent()
193 	u32 shift = GET_SHIFT(hwdata->conf);  in rzg2l_cpg_sd_clk_mux_set_parent()
208 	bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;  in rzg2l_cpg_sd_clk_mux_set_parent()
233 	struct sd_hw_data *hwdata = to_sd_hw_data(hw);  in rzg2l_cpg_sd_clk_mux_get_parent()  local
234 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_sd_clk_mux_get_parent()
235 	u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf));  in rzg2l_cpg_sd_clk_mux_get_parent()
237 	val >>= GET_SHIFT(hwdata->conf);  in rzg2l_cpg_sd_clk_mux_get_parent()
238 	val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);  in rzg2l_cpg_sd_clk_mux_get_parent()
442 	struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);  in rzg2l_cpg_pll5_4_clk_mux_determine_rate()  local
443 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_pll5_4_clk_mux_determine_rate()
454 	struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);  in rzg2l_cpg_pll5_4_clk_mux_set_parent()  local
455 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_pll5_4_clk_mux_set_parent()
475 	struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);  in rzg2l_cpg_pll5_4_clk_mux_get_parent()  local
476 	struct rzg2l_cpg_priv *priv = hwdata->priv;  in rzg2l_cpg_pll5_4_clk_mux_get_parent()
478 	return readl(priv->base + GET_REG_OFFSET(hwdata->conf));  in rzg2l_cpg_pll5_4_clk_mux_get_parent()