Lines Matching +full:0 +full:x610

19 #define RZV2M_SAMPLL4_CLK1	0x104
20 #define RZV2M_SAMPLL4_CLK2	0x108
24 #define DIV_A		DDIV_PACK(0x200, 0, 3)
25 #define DIV_B		DDIV_PACK(0x204, 0, 2)
26 #define DIV_E		DDIV_PACK(0x204, 8, 1)
27 #define DIV_W		DDIV_PACK(0x328, 0, 3)
29 #define SEL_B		SEL_PLL_PACK(0x214, 0, 1)
30 #define SEL_E		SEL_PLL_PACK(0x214, 2, 1)
31 #define SEL_W0		SEL_PLL_PACK(0x32C, 0, 1)
35 	LAST_DT_CORE_CLK = 0,
66 	{0, 1},
73 	{0, 0},
77 	{0, 1},
81 	{0, 0},
85 	{0, 6},
92 	{0, 0},
129 	DEF_MOD("pfc",		R9A09G011_PFC_PCLK,	 CLK_MAIN,     0x400, 2),
130 	DEF_MOD("gic",		R9A09G011_GIC_CLK,	 CLK_SEL_B_D2, 0x400, 5),
131 	DEF_COUPLED("eth_axi",	R9A09G011_ETH0_CLK_AXI,	 CLK_PLL2_200, 0x40c, 8),
132 	DEF_COUPLED("eth_chi",	R9A09G011_ETH0_CLK_CHI,	 CLK_PLL2_100, 0x40c, 8),
133 	DEF_MOD("eth_clk_gptp",	R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
134 	DEF_MOD("syc_cnt_clk",	R9A09G011_SYC_CNT_CLK,	 CLK_MAIN_24,  0x41c, 12),
135 	DEF_MOD("iic_pclk0",	R9A09G011_IIC_PCLK0,	 CLK_SEL_E,    0x420, 12),
136 	DEF_MOD("iic_pclk1",	R9A09G011_IIC_PCLK1,	 CLK_SEL_E,    0x424, 12),
137 	DEF_MOD("wdt0_pclk",	R9A09G011_WDT0_PCLK,	 CLK_SEL_E,    0x428, 12),
138 	DEF_MOD("wdt0_clk",	R9A09G011_WDT0_CLK,	 CLK_MAIN,     0x428, 13),
139 	DEF_MOD("urt_pclk",	R9A09G011_URT_PCLK,	 CLK_SEL_E,    0x438, 4),
140 	DEF_MOD("urt0_clk",	R9A09G011_URT0_CLK,	 CLK_SEL_W0,   0x438, 5),
141 	DEF_MOD("ca53",		R9A09G011_CA53_CLK,	 CLK_DIV_A,    0x448, 0),
145 	DEF_RST(R9A09G011_PFC_PRESETN,		0x600, 2),
146 	DEF_RST_MON(R9A09G011_ETH0_RST_HW_N,	0x608, 11, 11),
147 	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),
148 	DEF_RST(R9A09G011_IIC_GPA_PRESETN,	0x614, 8),
149 	DEF_RST(R9A09G011_IIC_GPB_PRESETN,	0x614, 9),
150 	DEF_RST_MON(R9A09G011_WDT0_PRESETN,	0x614, 12, 19),