38 	uint32_t managed: 1;
41 	uint32_t source : 8; /* source index + 1 (0 == none) */
56 			uint16_t group : 1;
68 		.source = 1 + R9A06G032_##_src, .name = _n, \
72 		.source = 1 + R9A06G032_##_src, .name = _n, \
73 		.managed = 1, .gate = I_GATE(__VA_ARGS__) }
79 		.source = 1 + R9A06G032_##_src, .name = _n, \
80 		.div = _div, .mul = 1}
83 		.source = 1 + R9A06G032_##_src, .name = _n, \
88 		.source = 1 + R9A06G032_##_src, .name = _n, \
132 #define R9A06G032_CLOCK_COUNT		(R9A06G032_UART_GROUP_34567 + 1)
135 	D_ROOT(CLKOUT, "clkout", 25, 1),
140 	D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
219 	D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
290 		.source = 1 + R9A06G032_DIV_UART,
299 		.source = 1 + R9A06G032_DIV_P2_PG,
302 		.dual.group = 1,
307 	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
308 	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
309 	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
310 	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
311 	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
352 	val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));  in clk_rdesc_set()
363 	return !!(val & (1U << (one & 0x1f)));  in clk_rdesc_get()
462 		       struct r9a06g032_gate *g, int on)  in r9a06g032_clk_gate_set()  argument
466 	WARN_ON(!g->gate);  in r9a06g032_clk_gate_set()
469 	clk_rdesc_set(clocks, g->gate, on);  in r9a06g032_clk_gate_set()
471 	if (g->reset)  in r9a06g032_clk_gate_set()
472 		clk_rdesc_set(clocks, g->reset, 1);  in r9a06g032_clk_gate_set()
482 	if (g->ready || g->midle) {  in r9a06g032_clk_gate_set()
484 		if (g->ready)  in r9a06g032_clk_gate_set()
485 			clk_rdesc_set(clocks, g->ready, on);  in r9a06g032_clk_gate_set()
487 		if (g->midle)  in r9a06g032_clk_gate_set()
488 			clk_rdesc_set(clocks, g->midle, !on);  in r9a06g032_clk_gate_set()
496 	struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);  in r9a06g032_clk_gate_enable()  local
498 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);  in r9a06g032_clk_gate_enable()
504 	struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);  in r9a06g032_clk_gate_disable()  local
506 	r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);  in r9a06g032_clk_gate_disable()
511 	struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);  in r9a06g032_clk_gate_is_enabled()  local
514 	if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))  in r9a06g032_clk_gate_is_enabled()
517 	return clk_rdesc_get(g->clocks, g->gate.gate);  in r9a06g032_clk_gate_is_enabled()
532 	struct r9a06g032_clk_gate *g;  in r9a06g032_register_gate()  local
535 	g = kzalloc(sizeof(*g), GFP_KERNEL);  in r9a06g032_register_gate()
536 	if (!g)  in r9a06g032_register_gate()
543 	init.num_parents = parent_name ? 1 : 0;  in r9a06g032_register_gate()
545 	g->clocks = clocks;  in r9a06g032_register_gate()
546 	g->index = desc->index;  in r9a06g032_register_gate()
547 	g->gate = desc->gate;  in r9a06g032_register_gate()
548 	g->hw.init = &init;  in r9a06g032_register_gate()
555 	if (r9a06g032_clk_gate_is_enabled(&g->hw)) {  in r9a06g032_register_gate()
560 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_gate()
562 		kfree(g);  in r9a06g032_register_gate()
606 	/* + 1 to cope with rates that have the remainder dropped */  in r9a06g032_div_clamp_div()
607 	u32 div = DIV_ROUND_UP(prate, rate + 1);  in r9a06g032_div_clamp_div()
615 	for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {  in r9a06g032_div_clamp_div()
616 		if (div >= clk->table[i] && div <= clk->table[i + 1]) {  in r9a06g032_div_clamp_div()
620 				DIV_ROUND_UP(prate, clk->table[i + 1]) -  in r9a06g032_div_clamp_div()
626 			div = p >= m ? clk->table[i] : clk->table[i + 1];  in r9a06g032_div_clamp_div()
672 	/* + 1 to cope with rates that have the remainder dropped */  in r9a06g032_div_set_rate()
673 	u32 div = DIV_ROUND_UP(parent_rate, rate + 1);  in r9a06g032_div_set_rate()
715 	init.num_parents = parent_name ? 1 : 0;  in r9a06g032_register_div()
787 	struct r9a06g032_clk_bitsel *g;  in r9a06g032_register_bitsel()  local
792 	g = kzalloc(sizeof(*g), GFP_KERNEL);  in r9a06g032_register_bitsel()
793 	if (!g)  in r9a06g032_register_bitsel()
797 	names[1] = "clk_pll_usb";  in r9a06g032_register_bitsel()
805 	g->clocks = clocks;  in r9a06g032_register_bitsel()
806 	g->index = desc->index;  in r9a06g032_register_bitsel()
807 	g->selector = desc->dual.sel;  in r9a06g032_register_bitsel()
808 	g->hw.init = &init;  in r9a06g032_register_bitsel()
810 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_bitsel()
812 		kfree(g);  in r9a06g032_register_bitsel()
830 r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable)  in r9a06g032_clk_dualgate_setenable()  argument
832 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);  in r9a06g032_clk_dualgate_setenable()
835 	r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);  in r9a06g032_clk_dualgate_setenable()
836 	r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);  in r9a06g032_clk_dualgate_setenable()
845 	r9a06g032_clk_dualgate_setenable(gate, 1);  in r9a06g032_clk_dualgate_enable()
859 	struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw);  in r9a06g032_clk_dualgate_is_enabled()  local
860 	u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);  in r9a06g032_clk_dualgate_is_enabled()
862 	return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);  in r9a06g032_clk_dualgate_is_enabled()
877 	struct r9a06g032_clk_dualgate *g;  in r9a06g032_register_dualgate()  local
882 	g = kzalloc(sizeof(*g), GFP_KERNEL);  in r9a06g032_register_dualgate()
883 	if (!g)  in r9a06g032_register_dualgate()
885 	g->clocks = clocks;  in r9a06g032_register_dualgate()
886 	g->index = desc->index;  in r9a06g032_register_dualgate()
887 	g->selector = sel;  in r9a06g032_register_dualgate()
888 	g->gate[0].gate = desc->dual.g1;  in r9a06g032_register_dualgate()
889 	g->gate[0].reset = desc->dual.r1;  in r9a06g032_register_dualgate()
890 	g->gate[1].gate = desc->dual.g2;  in r9a06g032_register_dualgate()
891 	g->gate[1].reset = desc->dual.r2;  in r9a06g032_register_dualgate()
897 	init.num_parents = 1;  in r9a06g032_register_dualgate()
898 	g->hw.init = &init;  in r9a06g032_register_dualgate()
904 	if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {  in r9a06g032_register_dualgate()
909 	clk = clk_register(NULL, &g->hw);  in r9a06g032_register_dualgate()
911 		kfree(g);  in r9a06g032_register_dualgate()
954 			__clk_get_name(clocks->data.clks[d->source - 1]) :  in r9a06g032_clocks_probe()