Lines Matching +full:0 +full:x160
78 DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
99 DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074),
100 DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078),
101 DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268),
102 DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c),
103 DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074),
104 DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078),
105 DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
106 DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
116 DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
117 DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
118 DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
119 DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
128 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
272 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
273 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
274 * 0 0 1 0 Prohibited setting
275 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
276 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
277 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
278 * 0 1 1 0 Prohibited setting
279 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
280 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
281 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
282 * 1 0 1 0 Prohibited setting
283 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
284 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
285 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
286 * 1 1 1 0 Prohibited setting
298 { 0, /* Prohibited setting */ },
302 { 0, /* Prohibited setting */ },
306 { 0, /* Prohibited setting */ },
310 { 0, /* Prohibited setting */ },
326 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); in r8a774e1_cpg_mssr_init()