Lines Matching full:div6
20 #include "clk-div6.h"
66 * DIV6 clocks require the divisor field to be non-zero when stopping in cpg_div6_clock_disable()
181 pr_err("%s: %s DIV6 clock set to invalid parent %u\n", in cpg_div6_clock_get_parent()
218 * TODO: This does not yet support DIV6 clocks with multiple in cpg_div6_clock_notifier_call()
220 * Fortunately so far such DIV6 clocks are found only on in cpg_div6_clock_notifier_call()
235 * cpg_div6_register - Register a DIV6 clock
236 * @name: Name of the DIV6 clock
237 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
239 * @reg: Mapped register used to control the DIV6 clock
280 pr_err("%s: invalid number of parents for DIV6 clock %s\n", in cpg_div6_register()
330 pr_err("%s: no parent found for %pOFn DIV6 clock\n", in cpg_div6_clock_init()
342 pr_err("%s: failed to map %pOFn DIV6 clock register\n", in cpg_div6_clock_init()
355 pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n", in cpg_div6_clock_init()
370 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);