Lines Matching +full:0 +full:x104c
65 { 1500000000, 2000000000, 0 },
71 { 1500000000, 2000000000, 0 },
75 { 500000000, 1500000000, 0 },
79 .offset = 0x0,
84 .enable_reg = 0x100,
85 .enable_mask = BIT(0),
98 .offset = 0x0,
113 .offset = 0x30,
118 .enable_reg = 0x100,
132 .offset = 0x30,
147 .offset = 0x4100,
162 .offset = 0x4100,
177 .offset = 0x60,
192 .offset = 0x60,
207 .offset = 0x90,
222 .offset = 0x90,
237 .offset = 0xc0,
252 .offset = 0xc0,
267 .offset = 0x4130,
282 .offset = 0x4130,
297 .offset = 0x4200,
312 .offset = 0x4200,
327 { P_XO, 0 },
337 { P_XO, 0 },
349 { P_XO, 0 },
361 { P_XO, 0 },
373 { P_XO, 0 },
387 { P_XO, 0 },
403 { P_XO, 0 },
419 { P_XO, 0 },
435 { P_XO, 0 },
451 { P_XO, 0 },
469 { P_XO, 0 },
489 { P_XO, 0 },
509 F(19200000, P_XO, 1, 0, 0),
510 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
511 F(80000000, P_MMPLL0, 10, 0, 0),
516 .cmd_rcgr = 0x5000,
529 F(19200000, P_XO, 1, 0, 0),
530 F(75000000, P_GPLL0_DIV, 4, 0, 0),
531 F(100000000, P_GPLL0, 6, 0, 0),
532 F(171430000, P_GPLL0, 3.5, 0, 0),
533 F(200000000, P_GPLL0, 3, 0, 0),
534 F(320000000, P_MMPLL0, 2.5, 0, 0),
535 F(400000000, P_MMPLL0, 2, 0, 0),
540 .cmd_rcgr = 0x5040,
553 .cmd_rcgr = 0x5090,
567 .cmd_rcgr = 0x4000,
586 F(19200000, P_XO, 1, 0, 0),
591 .cmd_rcgr = 0x4090,
604 .cmd_rcgr = 0x4010,
616 F(19200000, P_XO, 1, 0, 0),
617 F(50000000, P_GPLL0, 12, 0, 0),
622 .cmd_rcgr = 0x4060,
635 F(75000000, P_GPLL0_DIV, 4, 0, 0),
636 F(150000000, P_GPLL0, 4, 0, 0),
637 F(346666667, P_MMPLL3, 3, 0, 0),
638 F(520000000, P_MMPLL3, 2, 0, 0),
643 .cmd_rcgr = 0x1000,
657 .cmd_rcgr = 0x1060,
671 .cmd_rcgr = 0x1080,
685 .cmd_rcgr = 0x2000,
699 .cmd_rcgr = 0x2020,
713 F(85714286, P_GPLL0, 7, 0, 0),
714 F(100000000, P_GPLL0, 6, 0, 0),
715 F(150000000, P_GPLL0, 4, 0, 0),
716 F(171428571, P_GPLL0, 3.5, 0, 0),
717 F(200000000, P_GPLL0, 3, 0, 0),
718 F(275000000, P_MMPLL5, 3, 0, 0),
719 F(300000000, P_GPLL0, 2, 0, 0),
720 F(330000000, P_MMPLL5, 2.5, 0, 0),
721 F(412500000, P_MMPLL5, 2, 0, 0),
726 .cmd_rcgr = 0x2040,
744 .cmd_rcgr = 0x2060,
758 F(19200000, P_XO, 1, 0, 0),
763 .cmd_rcgr = 0x2080,
776 F(19200000, P_XO, 1, 0, 0),
781 .cmd_rcgr = 0x2100,
794 .cmd_rcgr = 0x2120,
807 .cmd_rcgr = 0x2140,
820 F(19200000, P_XO, 1, 0, 0),
825 .cmd_rcgr = 0x2160,
838 .cmd_rcgr = 0x2180,
861 .cmd_rcgr = 0x3420,
875 .cmd_rcgr = 0x3450,
889 F(4800000, P_XO, 4, 0, 0),
892 F(9600000, P_XO, 2, 0, 0),
894 F(19200000, P_XO, 1, 0, 0),
903 .cmd_rcgr = 0x3360,
917 .cmd_rcgr = 0x3390,
931 .cmd_rcgr = 0x33c0,
945 .cmd_rcgr = 0x33f0,
959 F(19200000, P_XO, 1, 0, 0),
960 F(37500000, P_GPLL0, 16, 0, 0),
961 F(50000000, P_GPLL0, 12, 0, 0),
962 F(100000000, P_GPLL0, 6, 0, 0),
967 .cmd_rcgr = 0x3300,
981 F(100000000, P_GPLL0_DIV, 3, 0, 0),
982 F(200000000, P_GPLL0, 3, 0, 0),
983 F(266666667, P_MMPLL0, 3, 0, 0),
988 .cmd_rcgr = 0x3000,
1001 .cmd_rcgr = 0x3030,
1014 .cmd_rcgr = 0x3060,
1027 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1028 F(200000000, P_GPLL0, 3, 0, 0),
1029 F(320000000, P_MMPLL4, 3, 0, 0),
1030 F(384000000, P_MMPLL4, 2.5, 0, 0),
1035 .cmd_rcgr = 0x3240,
1048 .cmd_rcgr = 0x3260,
1061 .cmd_rcgr = 0x3280,
1074 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1075 F(150000000, P_GPLL0, 4, 0, 0),
1076 F(228571429, P_MMPLL0, 3.5, 0, 0),
1077 F(266666667, P_MMPLL0, 3, 0, 0),
1078 F(320000000, P_MMPLL0, 2.5, 0, 0),
1079 F(480000000, P_MMPLL4, 2, 0, 0),
1084 .cmd_rcgr = 0x3500,
1097 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1098 F(150000000, P_GPLL0, 4, 0, 0),
1099 F(228571429, P_MMPLL0, 3.5, 0, 0),
1100 F(266666667, P_MMPLL0, 3, 0, 0),
1101 F(320000000, P_MMPLL0, 2.5, 0, 0),
1106 .cmd_rcgr = 0x3540,
1119 .cmd_rcgr = 0x3560,
1132 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1133 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1134 F(300000000, P_GPLL0, 2, 0, 0),
1135 F(320000000, P_MMPLL0, 2.5, 0, 0),
1136 F(480000000, P_MMPLL4, 2, 0, 0),
1137 F(600000000, P_GPLL0, 1, 0, 0),
1142 .cmd_rcgr = 0x3600,
1155 .cmd_rcgr = 0x3620,
1168 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1169 F(200000000, P_GPLL0, 3, 0, 0),
1170 F(320000000, P_MMPLL0, 2.5, 0, 0),
1171 F(480000000, P_MMPLL4, 2, 0, 0),
1172 F(640000000, P_MMPLL4, 1.5, 0, 0),
1177 .cmd_rcgr = 0x3640,
1190 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1191 F(200000000, P_GPLL0, 3, 0, 0),
1192 F(266666667, P_MMPLL0, 3, 0, 0),
1193 F(480000000, P_MMPLL4, 2, 0, 0),
1194 F(600000000, P_GPLL0, 1, 0, 0),
1199 .cmd_rcgr = 0x3090,
1212 .cmd_rcgr = 0x3100,
1225 .cmd_rcgr = 0x3160,
1238 .cmd_rcgr = 0x31c0,
1251 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1252 F(200000000, P_GPLL0, 3, 0, 0),
1253 F(400000000, P_MMPLL0, 2, 0, 0),
1258 .cmd_rcgr = 0x3b00,
1271 .halt_reg = 0x5024,
1273 .enable_reg = 0x5024,
1274 .enable_mask = BIT(0),
1288 .halt_reg = 0x5054,
1290 .enable_reg = 0x5054,
1291 .enable_mask = BIT(0),
1305 .halt_reg = 0x5018,
1307 .enable_reg = 0x5018,
1308 .enable_mask = BIT(0),
1322 .halt_reg = 0x5014,
1324 .enable_reg = 0x5014,
1325 .enable_mask = BIT(0),
1338 .halt_reg = 0x5074,
1340 .enable_reg = 0x5074,
1341 .enable_mask = BIT(0),
1355 .halt_reg = 0x3c44,
1357 .enable_reg = 0x3c44,
1358 .enable_mask = BIT(0),
1372 .halt_reg = 0x3c48,
1374 .enable_reg = 0x3c48,
1375 .enable_mask = BIT(0),
1389 .halt_reg = 0x3c04,
1391 .enable_reg = 0x3c04,
1392 .enable_mask = BIT(0),
1406 .halt_reg = 0x3c08,
1408 .enable_reg = 0x3c08,
1409 .enable_mask = BIT(0),
1423 .halt_reg = 0x3c14,
1425 .enable_reg = 0x3c14,
1426 .enable_mask = BIT(0),
1440 .halt_reg = 0x3c18,
1442 .enable_reg = 0x3c18,
1443 .enable_mask = BIT(0),
1457 .halt_reg = 0x3c24,
1459 .enable_reg = 0x3c24,
1460 .enable_mask = BIT(0),
1474 .halt_reg = 0x3c28,
1476 .enable_reg = 0x3c28,
1477 .enable_mask = BIT(0),
1491 .halt_reg = 0x2474,
1493 .enable_reg = 0x2474,
1494 .enable_mask = BIT(0),
1508 .halt_reg = 0x2478,
1510 .enable_reg = 0x2478,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0x2444,
1527 .enable_reg = 0x2444,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0x2448,
1544 .enable_reg = 0x2448,
1545 .enable_mask = BIT(0),
1559 .halt_reg = 0x2454,
1561 .enable_reg = 0x2454,
1562 .enable_mask = BIT(0),
1576 .halt_reg = 0x2458,
1578 .enable_reg = 0x2458,
1579 .enable_mask = BIT(0),
1593 .halt_reg = 0x1194,
1595 .enable_reg = 0x1194,
1596 .enable_mask = BIT(0),
1610 .halt_reg = 0x1198,
1612 .enable_reg = 0x1198,
1613 .enable_mask = BIT(0),
1627 .halt_reg = 0x1174,
1629 .enable_reg = 0x1174,
1630 .enable_mask = BIT(0),
1644 .halt_reg = 0x1178,
1646 .enable_reg = 0x1178,
1647 .enable_mask = BIT(0),
1661 .halt_reg = 0x5298,
1663 .enable_reg = 0x5298,
1664 .enable_mask = BIT(0),
1678 .halt_reg = 0x4028,
1680 .enable_reg = 0x4028,
1681 .enable_mask = BIT(0),
1695 .halt_reg = 0x40b0,
1697 .enable_reg = 0x40b0,
1698 .enable_mask = BIT(0),
1712 .halt_reg = 0x403c,
1714 .enable_reg = 0x403c,
1715 .enable_mask = BIT(0),
1729 .halt_reg = 0x4044,
1731 .enable_reg = 0x4044,
1732 .enable_mask = BIT(0),
1746 .halt_reg = 0x1204,
1748 .enable_reg = 0x1204,
1749 .enable_mask = BIT(0),
1763 .halt_reg = 0x1208,
1765 .enable_reg = 0x1208,
1766 .enable_mask = BIT(0),
1780 .halt_reg = 0x4084,
1782 .enable_reg = 0x4084,
1783 .enable_mask = BIT(0),
1797 .halt_reg = 0x4088,
1799 .enable_reg = 0x4088,
1800 .enable_mask = BIT(0),
1814 .halt_reg = 0x1028,
1816 .enable_reg = 0x1028,
1817 .enable_mask = BIT(0),
1831 .halt_reg = 0x1034,
1833 .enable_reg = 0x1034,
1834 .enable_mask = BIT(0),
1848 .halt_reg = 0x1038,
1850 .enable_reg = 0x1038,
1851 .enable_mask = BIT(0),
1865 .halt_reg = 0x1030,
1867 .enable_reg = 0x1030,
1868 .enable_mask = BIT(0),
1882 .halt_reg = 0x1048,
1884 .enable_reg = 0x1048,
1885 .enable_mask = BIT(0),
1899 .halt_reg = 0x104c,
1901 .enable_reg = 0x104c,
1902 .enable_mask = BIT(0),
1916 .halt_reg = 0x2308,
1918 .enable_reg = 0x2308,
1919 .enable_mask = BIT(0),
1933 .halt_reg = 0x230c,
1935 .enable_reg = 0x230c,
1936 .enable_mask = BIT(0),
1950 .halt_reg = 0x2310,
1952 .enable_reg = 0x2310,
1953 .enable_mask = BIT(0),
1967 .halt_reg = 0x2314,
1969 .enable_reg = 0x2314,
1970 .enable_mask = BIT(0),
1984 .halt_reg = 0x2318,
1986 .enable_reg = 0x2318,
1987 .enable_mask = BIT(0),
2001 .halt_reg = 0x231c,
2003 .enable_reg = 0x231c,
2004 .enable_mask = BIT(0),
2018 .halt_reg = 0x2324,
2020 .enable_reg = 0x2324,
2021 .enable_mask = BIT(0),
2035 .halt_reg = 0x2328,
2037 .enable_reg = 0x2328,
2038 .enable_mask = BIT(0),
2052 .halt_reg = 0x2338,
2054 .enable_reg = 0x2338,
2055 .enable_mask = BIT(0),
2069 .halt_reg = 0x233c,
2071 .enable_reg = 0x233c,
2072 .enable_mask = BIT(0),
2086 .halt_reg = 0x2340,
2088 .enable_reg = 0x2340,
2089 .enable_mask = BIT(0),
2103 .halt_reg = 0x2344,
2105 .enable_reg = 0x2344,
2106 .enable_mask = BIT(0),
2120 .halt_reg = 0x2348,
2122 .enable_reg = 0x2348,
2123 .enable_mask = BIT(0),
2137 .halt_reg = 0x3484,
2139 .enable_reg = 0x3484,
2140 .enable_mask = BIT(0),
2154 .halt_reg = 0x348c,
2156 .enable_reg = 0x348c,
2157 .enable_mask = BIT(0),
2171 .halt_reg = 0x3494,
2173 .enable_reg = 0x3494,
2174 .enable_mask = BIT(0),
2188 .halt_reg = 0x3444,
2190 .enable_reg = 0x3444,
2191 .enable_mask = BIT(0),
2205 .halt_reg = 0x3474,
2207 .enable_reg = 0x3474,
2208 .enable_mask = BIT(0),
2222 .halt_reg = 0x3384,
2224 .enable_reg = 0x3384,
2225 .enable_mask = BIT(0),
2239 .halt_reg = 0x33b4,
2241 .enable_reg = 0x33b4,
2242 .enable_mask = BIT(0),
2256 .halt_reg = 0x33e4,
2258 .enable_reg = 0x33e4,
2259 .enable_mask = BIT(0),
2273 .halt_reg = 0x3414,
2275 .enable_reg = 0x3414,
2276 .enable_mask = BIT(0),
2290 .halt_reg = 0x3344,
2292 .enable_reg = 0x3344,
2293 .enable_mask = BIT(0),
2307 .halt_reg = 0x3348,
2309 .enable_reg = 0x3348,
2310 .enable_mask = BIT(0),
2324 .halt_reg = 0x3024,
2326 .enable_reg = 0x3024,
2327 .enable_mask = BIT(0),
2341 .halt_reg = 0x3054,
2343 .enable_reg = 0x3054,
2344 .enable_mask = BIT(0),
2358 .halt_reg = 0x3084,
2360 .enable_reg = 0x3084,
2361 .enable_mask = BIT(0),
2375 .halt_reg = 0x3234,
2377 .enable_reg = 0x3234,
2378 .enable_mask = BIT(0),
2392 .halt_reg = 0x3254,
2394 .enable_reg = 0x3254,
2395 .enable_mask = BIT(0),
2409 .halt_reg = 0x3274,
2411 .enable_reg = 0x3274,
2412 .enable_mask = BIT(0),
2426 .halt_reg = 0x35a8,
2428 .enable_reg = 0x35a8,
2429 .enable_mask = BIT(0),
2443 .halt_reg = 0x35b0,
2445 .enable_reg = 0x35b0,
2446 .enable_mask = BIT(0),
2460 .halt_reg = 0x35c0,
2462 .enable_reg = 0x35c0,
2463 .enable_mask = BIT(0),
2477 .halt_reg = 0x35b4,
2479 .enable_reg = 0x35b4,
2480 .enable_mask = BIT(0),
2494 .halt_reg = 0x35b8,
2496 .enable_reg = 0x35b8,
2497 .enable_mask = BIT(0),
2511 .halt_reg = 0x36b8,
2513 .enable_reg = 0x36b8,
2514 .enable_mask = BIT(0),
2528 .halt_reg = 0x36bc,
2530 .enable_reg = 0x36bc,
2531 .enable_mask = BIT(0),
2545 .halt_reg = 0x36a8,
2547 .enable_reg = 0x36a8,
2548 .enable_mask = BIT(0),
2562 .halt_reg = 0x3720,
2564 .enable_reg = 0x3720,
2565 .enable_mask = BIT(0),
2579 .halt_reg = 0x3668,
2581 .enable_reg = 0x3668,
2582 .enable_mask = BIT(0),
2596 .halt_reg = 0x36ac,
2598 .enable_reg = 0x36ac,
2599 .enable_mask = BIT(0),
2613 .halt_reg = 0x3724,
2615 .enable_reg = 0x3724,
2616 .enable_mask = BIT(0),
2630 .halt_reg = 0x3678,
2632 .enable_reg = 0x3678,
2633 .enable_mask = BIT(0),
2647 .halt_reg = 0x3704,
2649 .enable_reg = 0x3704,
2650 .enable_mask = BIT(0),
2664 .halt_reg = 0x3714,
2666 .enable_reg = 0x3714,
2667 .enable_mask = BIT(0),
2681 .halt_reg = 0x36c8,
2683 .enable_reg = 0x36c8,
2684 .enable_mask = BIT(0),
2698 .halt_reg = 0x36c4,
2700 .enable_reg = 0x36c4,
2701 .enable_mask = BIT(0),
2715 .halt_reg = 0x36b0,
2717 .enable_reg = 0x36b0,
2718 .enable_mask = BIT(0),
2732 .halt_reg = 0x36b4,
2734 .enable_reg = 0x36b4,
2735 .enable_mask = BIT(0),
2749 .halt_reg = 0x30b4,
2751 .enable_reg = 0x30b4,
2752 .enable_mask = BIT(0),
2766 .halt_reg = 0x30bc,
2768 .enable_reg = 0x30bc,
2769 .enable_mask = BIT(0),
2783 .halt_reg = 0x30c4,
2785 .enable_reg = 0x30c4,
2786 .enable_mask = BIT(0),
2800 .halt_reg = 0x30d4,
2802 .enable_reg = 0x30d4,
2803 .enable_mask = BIT(0),
2817 .halt_reg = 0x30e4,
2819 .enable_reg = 0x30e4,
2820 .enable_mask = BIT(0),
2834 .halt_reg = 0x3124,
2836 .enable_reg = 0x3124,
2837 .enable_mask = BIT(0),
2851 .halt_reg = 0x3128,
2853 .enable_reg = 0x3128,
2854 .enable_mask = BIT(0),
2868 .halt_reg = 0x3134,
2870 .enable_reg = 0x3134,
2871 .enable_mask = BIT(0),
2885 .halt_reg = 0x3144,
2887 .enable_reg = 0x3144,
2888 .enable_mask = BIT(0),
2902 .halt_reg = 0x3154,
2904 .enable_reg = 0x3154,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x3184,
2921 .enable_reg = 0x3184,
2922 .enable_mask = BIT(0),
2936 .halt_reg = 0x3188,
2938 .enable_reg = 0x3188,
2939 .enable_mask = BIT(0),
2953 .halt_reg = 0x3194,
2955 .enable_reg = 0x3194,
2956 .enable_mask = BIT(0),
2970 .halt_reg = 0x31a4,
2972 .enable_reg = 0x31a4,
2973 .enable_mask = BIT(0),
2987 .halt_reg = 0x31b4,
2989 .enable_reg = 0x31b4,
2990 .enable_mask = BIT(0),
3004 .halt_reg = 0x31e4,
3006 .enable_reg = 0x31e4,
3007 .enable_mask = BIT(0),
3021 .halt_reg = 0x31e8,
3023 .enable_reg = 0x31e8,
3024 .enable_mask = BIT(0),
3038 .halt_reg = 0x31f4,
3040 .enable_reg = 0x31f4,
3041 .enable_mask = BIT(0),
3055 .halt_reg = 0x3204,
3057 .enable_reg = 0x3204,
3058 .enable_mask = BIT(0),
3072 .halt_reg = 0x3214,
3074 .enable_reg = 0x3214,
3075 .enable_mask = BIT(0),
3089 .halt_reg = 0x3224,
3091 .enable_reg = 0x3224,
3092 .enable_mask = BIT(0),
3106 .halt_reg = 0x3b68,
3108 .enable_reg = 0x3b68,
3109 .enable_mask = BIT(0),
3123 .halt_reg = 0x3b6c,
3125 .enable_reg = 0x3b6c,
3126 .enable_mask = BIT(0),
3140 .halt_reg = 0x3ba74,
3142 .enable_reg = 0x3ba74,
3143 .enable_mask = BIT(0),
3161 .gdscr = 0x529c,
3170 .gdscr = 0x119c,
3171 .gds_hw_ctrl = 0x120c,
3180 .gdscr = 0x247c,
3181 .gds_hw_ctrl = 0x2480,
3190 .gdscr = 0x3c4c,
3191 .gds_hw_ctrl = 0x3c50,
3200 .gdscr = 0x1024,
3201 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
3211 .gdscr = 0x1040,
3212 .cxcs = (unsigned int []){ 0x1048 },
3223 .gdscr = 0x1044,
3224 .cxcs = (unsigned int []){ 0x104c },
3235 .gdscr = 0x34a0,
3236 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
3246 .gdscr = 0x3664,
3247 .cxcs = (unsigned int []){ 0x36a8 },
3257 .gdscr = 0x3674,
3258 .cxcs = (unsigned int []){ 0x36ac },
3268 .gdscr = 0x35a4,
3269 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3279 .gdscr = 0x36d4,
3280 .cxcs = (unsigned int []){ 0x36b0 },
3290 .gdscr = 0x3b64,
3291 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3301 .gdscr = 0x2304,
3302 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3312 .gdscr = 0x4034,
3313 .gds_hw_ctrl = 0x4038,
3322 .gdscr = 0x4024,
3323 .clamp_io_ctrl = 0x4300,
3324 .cxcs = (unsigned int []){ 0x4028 },
3529 [MMAGICAHB_BCR] = { 0x5020 },
3530 [MMAGIC_CFG_BCR] = { 0x5050 },
3531 [MISC_BCR] = { 0x5010 },
3532 [BTO_BCR] = { 0x5030 },
3533 [MMAGICAXI_BCR] = { 0x5060 },
3534 [MMAGICMAXI_BCR] = { 0x5070 },
3535 [DSA_BCR] = { 0x50a0 },
3536 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3537 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3538 [SMMU_VFE_BCR] = { 0x3c00 },
3539 [SMMU_CPP_BCR] = { 0x3c10 },
3540 [SMMU_JPEG_BCR] = { 0x3c20 },
3541 [MMAGIC_MDSS_BCR] = { 0x2470 },
3542 [THROTTLE_MDSS_BCR] = { 0x2460 },
3543 [SMMU_ROT_BCR] = { 0x2440 },
3544 [SMMU_MDP_BCR] = { 0x2450 },
3545 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3546 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3547 [SMMU_VIDEO_BCR] = { 0x1170 },
3548 [MMAGIC_BIMC_BCR] = { 0x5290 },
3549 [GPU_GX_BCR] = { 0x4020 },
3550 [GPU_BCR] = { 0x4030 },
3551 [GPU_AON_BCR] = { 0x4040 },
3552 [VMEM_BCR] = { 0x1200 },
3553 [MMSS_RBCPR_BCR] = { 0x4080 },
3554 [VIDEO_BCR] = { 0x1020 },
3555 [MDSS_BCR] = { 0x2300 },
3556 [CAMSS_TOP_BCR] = { 0x3480 },
3557 [CAMSS_AHB_BCR] = { 0x3488 },
3558 [CAMSS_MICRO_BCR] = { 0x3490 },
3559 [CAMSS_CCI_BCR] = { 0x3340 },
3560 [CAMSS_PHY0_BCR] = { 0x3020 },
3561 [CAMSS_PHY1_BCR] = { 0x3050 },
3562 [CAMSS_PHY2_BCR] = { 0x3080 },
3563 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3564 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3565 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3566 [CAMSS_JPEG_BCR] = { 0x35a0 },
3567 [CAMSS_VFE_BCR] = { 0x36a0 },
3568 [CAMSS_VFE0_BCR] = { 0x3660 },
3569 [CAMSS_VFE1_BCR] = { 0x3670 },
3570 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3571 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3572 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3573 [CAMSS_CPP_BCR] = { 0x36d0 },
3574 [CAMSS_CSI0_BCR] = { 0x30b0 },
3575 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3576 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3577 [CAMSS_CSI1_BCR] = { 0x3120 },
3578 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3579 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3580 [CAMSS_CSI2_BCR] = { 0x3180 },
3581 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3582 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3583 [CAMSS_CSI3_BCR] = { 0x31e0 },
3584 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3585 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3586 [CAMSS_ISPIF_BCR] = { 0x3220 },
3587 [FD_BCR] = { 0x3b60 },
3588 [MMSS_SPDM_RM_BCR] = { 0x300 },
3595 .max_register = 0xb008,
3626 regmap_update_bits(regmap, 0x50d8, BIT(31), 0); in mmcc_msm8996_probe()
3628 regmap_update_bits(regmap, 0x5054, BIT(15), 0); in mmcc_msm8996_probe()