Lines Matching +full:0 +full:x104c
45 { P_XO, 0 },
55 { P_XO, 0 },
65 { P_XO, 0 },
77 { P_XO, 0 },
92 { 1500000000, 2000000000, 0 },
96 { 500000000, 1500000000, 0 },
100 .post_div_mask = 0xf00,
104 .offset = 0x0,
109 .enable_reg = 0x100,
110 .enable_mask = BIT(0),
123 .offset = 0x0,
136 .offset = 0x30,
141 .enable_reg = 0x100,
155 .offset = 0x30,
168 .offset = 0x60,
183 .offset = 0x60,
196 .offset = 0x90,
211 .offset = 0x90,
224 { P_XO, 0 },
236 { P_XO, 0 },
248 { P_XO, 0 },
262 { P_XO, 0 },
276 .offset = 0xc0,
291 .offset = 0xc0,
305 F(19200000, P_XO, 1, 0, 0),
306 F(40000000, P_GPLL0, 15, 0, 0),
307 F(80000000, P_MMPLL0, 10, 0, 0),
312 .cmd_rcgr = 0x5000,
325 F(75000000, P_GPLL0, 8, 0, 0),
326 F(150000000, P_GPLL0, 4, 0, 0),
327 F(333430000, P_MMPLL1, 3.5, 0, 0),
328 F(466800000, P_MMPLL1, 2.5, 0, 0),
333 F(75000000, P_GPLL0, 8, 0, 0),
334 F(150000000, P_GPLL0, 4, 0, 0),
335 F(300000000, P_GPLL0, 2, 0, 0),
336 F(404000000, P_MMPLL1, 2, 0, 0),
341 .cmd_rcgr = 0x5040,
354 F(100000000, P_GPLL0, 6, 0, 0),
355 F(240000000, P_GPLL0, 2.5, 0, 0),
356 F(266670000, P_MMPLL0, 3, 0, 0),
361 F(100000000, P_GPLL0, 6, 0, 0),
362 F(266670000, P_MMPLL0, 3, 0, 0),
367 .cmd_rcgr = 0x3090,
380 F(66670000, P_GPLL0, 9, 0, 0),
381 F(100000000, P_GPLL0, 6, 0, 0),
382 F(133330000, P_GPLL0, 4.5, 0, 0),
383 F(150000000, P_GPLL0, 4, 0, 0),
384 F(200000000, P_MMPLL0, 4, 0, 0),
385 F(240000000, P_GPLL0, 2.5, 0, 0),
386 F(266670000, P_MMPLL0, 3, 0, 0),
387 F(320000000, P_MMPLL0, 2.5, 0, 0),
388 F(510000000, P_MMPLL3, 2, 0, 0),
393 F(66670000, P_GPLL0, 9, 0, 0),
394 F(100000000, P_GPLL0, 6, 0, 0),
395 F(133330000, P_GPLL0, 4.5, 0, 0),
396 F(200000000, P_MMPLL0, 4, 0, 0),
397 F(320000000, P_MMPLL0, 2.5, 0, 0),
398 F(510000000, P_MMPLL3, 2, 0, 0),
403 .cmd_rcgr = 0x1000,
417 .cmd_rcgr = 0x3100,
430 .cmd_rcgr = 0x3160,
443 .cmd_rcgr = 0x31c0,
456 F(80000000, P_GPLL0, 7.5, 0, 0),
457 F(100000000, P_GPLL0, 6, 0, 0),
458 F(200000000, P_GPLL0, 3, 0, 0),
459 F(320000000, P_MMPLL0, 2.5, 0, 0),
460 F(400000000, P_MMPLL0, 2, 0, 0),
461 F(480000000, P_MMPLL4, 2, 0, 0),
462 F(533330000, P_MMPLL0, 1.5, 0, 0),
463 F(600000000, P_GPLL0, 1, 0, 0),
468 F(80000000, P_GPLL0, 7.5, 0, 0),
469 F(100000000, P_GPLL0, 6, 0, 0),
470 F(200000000, P_GPLL0, 3, 0, 0),
471 F(320000000, P_MMPLL0, 2.5, 0, 0),
472 F(480000000, P_MMPLL4, 2, 0, 0),
473 F(600000000, P_GPLL0, 1, 0, 0),
478 .cmd_rcgr = 0x3600,
491 F(80000000, P_GPLL0, 7.5, 0, 0),
492 F(100000000, P_GPLL0, 6, 0, 0),
493 F(200000000, P_GPLL0, 3, 0, 0),
494 F(320000000, P_MMPLL0, 2.5, 0, 0),
495 F(400000000, P_MMPLL0, 2, 0, 0),
496 F(533330000, P_MMPLL0, 1.5, 0, 0),
501 .cmd_rcgr = 0x3620,
514 F(100000000, P_GPLL0, 6, 0, 0),
515 F(200000000, P_GPLL0, 3, 0, 0),
516 F(320000000, P_MMPLL0, 2.5, 0, 0),
517 F(480000000, P_MMPLL4, 2, 0, 0),
518 F(600000000, P_GPLL0, 1, 0, 0),
519 F(640000000, P_MMPLL4, 1.5, 0, 0),
524 F(100000000, P_GPLL0, 6, 0, 0),
525 F(200000000, P_GPLL0, 3, 0, 0),
526 F(320000000, P_MMPLL0, 2.5, 0, 0),
527 F(480000000, P_MMPLL4, 2, 0, 0),
528 F(640000000, P_MMPLL4, 1.5, 0, 0),
533 .cmd_rcgr = 0x3640,
546 F(75000000, P_GPLL0, 8, 0, 0),
547 F(150000000, P_GPLL0, 4, 0, 0),
548 F(228570000, P_MMPLL0, 3.5, 0, 0),
549 F(266670000, P_MMPLL0, 3, 0, 0),
550 F(320000000, P_MMPLL0, 2.5, 0, 0),
551 F(480000000, P_MMPLL4, 2, 0, 0),
556 .cmd_rcgr = 0x3520,
569 F(75000000, P_GPLL0, 8, 0, 0),
570 F(133330000, P_GPLL0, 4.5, 0, 0),
571 F(150000000, P_GPLL0, 4, 0, 0),
572 F(228570000, P_MMPLL0, 3.5, 0, 0),
573 F(266670000, P_MMPLL0, 3, 0, 0),
574 F(320000000, P_MMPLL0, 2.5, 0, 0),
579 .cmd_rcgr = 0x3540,
592 F(50000000, P_GPLL0, 12, 0, 0),
593 F(100000000, P_GPLL0, 6, 0, 0),
594 F(200000000, P_MMPLL0, 4, 0, 0),
599 .cmd_rcgr = 0x3060,
612 F(60000000, P_GPLL0, 10, 0, 0),
613 F(200000000, P_GPLL0, 3, 0, 0),
614 F(320000000, P_MMPLL0, 2.5, 0, 0),
615 F(400000000, P_MMPLL0, 2, 0, 0),
620 .cmd_rcgr = 0x3b00,
633 F(85710000, P_GPLL0, 7, 0, 0),
634 F(100000000, P_GPLL0, 6, 0, 0),
635 F(120000000, P_GPLL0, 5, 0, 0),
636 F(150000000, P_GPLL0, 4, 0, 0),
637 F(171430000, P_GPLL0, 3.5, 0, 0),
638 F(200000000, P_GPLL0, 3, 0, 0),
639 F(240000000, P_GPLL0, 2.5, 0, 0),
640 F(266670000, P_MMPLL0, 3, 0, 0),
641 F(300000000, P_GPLL0, 2, 0, 0),
642 F(320000000, P_MMPLL0, 2.5, 0, 0),
643 F(400000000, P_MMPLL0, 2, 0, 0),
648 F(85710000, P_GPLL0, 7, 0, 0),
649 F(171430000, P_GPLL0, 3.5, 0, 0),
650 F(200000000, P_GPLL0, 3, 0, 0),
651 F(240000000, P_GPLL0, 2.5, 0, 0),
652 F(266670000, P_MMPLL0, 3, 0, 0),
653 F(320000000, P_MMPLL0, 2.5, 0, 0),
654 F(400000000, P_MMPLL0, 2, 0, 0),
659 .cmd_rcgr = 0x2040,
672 .cmd_rcgr = 0x2000,
686 .cmd_rcgr = 0x2020,
700 F(19200000, P_XO, 1, 0, 0),
701 F(75000000, P_GPLL0, 8, 0, 0),
702 F(100000000, P_GPLL0, 6, 0, 0),
703 F(150000000, P_GPLL0, 4, 0, 0),
704 F(228570000, P_MMPLL0, 3.5, 0, 0),
705 F(266670000, P_MMPLL0, 3, 0, 0),
706 F(320000000, P_MMPLL0, 2.5, 0, 0),
707 F(400000000, P_MMPLL0, 2, 0, 0),
712 F(19200000, P_XO, 1, 0, 0),
713 F(75000000, P_GPLL0, 8, 0, 0),
714 F(100000000, P_GPLL0, 6, 0, 0),
715 F(150000000, P_GPLL0, 4, 0, 0),
716 F(320000000, P_MMPLL0, 2.5, 0, 0),
717 F(400000000, P_MMPLL0, 2, 0, 0),
722 .cmd_rcgr = 0x5090,
735 F(19200000, P_XO, 1, 0, 0),
736 F(37500000, P_GPLL0, 16, 0, 0),
737 F(50000000, P_GPLL0, 12, 0, 0),
738 F(100000000, P_GPLL0, 6, 0, 0),
743 .cmd_rcgr = 0x3300,
767 .cmd_rcgr = 0x3420,
781 .cmd_rcgr = 0x3450,
795 .cmd_rcgr = 0x3500,
808 .cmd_rcgr = 0x3560,
821 F(4800000, P_XO, 4, 0, 0),
824 F(9600000, P_XO, 2, 0, 0),
826 F(19200000, P_XO, 1, 0, 0),
829 F(48000000, P_GPLL0, 12.5, 0, 0),
830 F(64000000, P_MMPLL0, 12.5, 0, 0),
835 F(4800000, P_XO, 4, 0, 0),
838 F(9600000, P_XO, 2, 0, 0),
841 F(19200000, P_XO, 1, 0, 0),
845 F(64000000, P_MMPLL4, 15, 0, 0),
850 F(4800000, P_XO, 4, 0, 0),
853 F(9600000, P_XO, 2, 0, 0),
855 F(19200000, P_XO, 1, 0, 0),
859 F(64000000, P_MMPLL4, 15, 0, 0),
864 .cmd_rcgr = 0x3360,
878 .cmd_rcgr = 0x3390,
892 .cmd_rcgr = 0x33c0,
906 .cmd_rcgr = 0x33f0,
920 F(50000000, P_GPLL0, 12, 0, 0),
921 F(100000000, P_GPLL0, 6, 0, 0),
922 F(200000000, P_MMPLL0, 4, 0, 0),
927 .cmd_rcgr = 0x3000,
940 .cmd_rcgr = 0x3030,
953 .cmd_rcgr = 0x2120,
966 .cmd_rcgr = 0x2140,
979 F(19200000, P_XO, 1, 0, 0),
984 .cmd_rcgr = 0x2160,
997 .cmd_rcgr = 0x2180,
1015 .cmd_rcgr = 0x2060,
1029 F(19200000, P_XO, 1, 0, 0),
1034 .cmd_rcgr = 0x2100,
1047 F(19200000, P_XO, 1, 0, 0),
1052 .cmd_rcgr = 0x2080,
1065 F(19200000, P_XO, 1, 0, 0),
1070 .cmd_rcgr = 0x4090,
1083 .halt_reg = 0x348c,
1085 .enable_reg = 0x348c,
1086 .enable_mask = BIT(0),
1098 .halt_reg = 0x3348,
1100 .enable_reg = 0x3348,
1101 .enable_mask = BIT(0),
1113 .halt_reg = 0x3344,
1115 .enable_reg = 0x3344,
1116 .enable_mask = BIT(0),
1127 .halt_reg = 0x36b4,
1129 .enable_reg = 0x36b4,
1130 .enable_mask = BIT(0),
1142 .halt_reg = 0x36c4,
1144 .enable_reg = 0x36c4,
1145 .enable_mask = BIT(0),
1156 .halt_reg = 0x36b0,
1158 .enable_reg = 0x36b0,
1159 .enable_mask = BIT(0),
1170 .halt_reg = 0x30bc,
1172 .enable_reg = 0x30bc,
1173 .enable_mask = BIT(0),
1185 .halt_reg = 0x30b4,
1187 .enable_reg = 0x30b4,
1188 .enable_mask = BIT(0),
1199 .halt_reg = 0x30c4,
1201 .enable_reg = 0x30c4,
1202 .enable_mask = BIT(0),
1213 .halt_reg = 0x30e4,
1215 .enable_reg = 0x30e4,
1216 .enable_mask = BIT(0),
1227 .halt_reg = 0x30d4,
1229 .enable_reg = 0x30d4,
1230 .enable_mask = BIT(0),
1241 .halt_reg = 0x3128,
1243 .enable_reg = 0x3128,
1244 .enable_mask = BIT(0),
1256 .halt_reg = 0x3124,
1258 .enable_reg = 0x3124,
1259 .enable_mask = BIT(0),
1270 .halt_reg = 0x3134,
1272 .enable_reg = 0x3134,
1273 .enable_mask = BIT(0),
1284 .halt_reg = 0x3154,
1286 .enable_reg = 0x3154,
1287 .enable_mask = BIT(0),
1298 .halt_reg = 0x3144,
1300 .enable_reg = 0x3144,
1301 .enable_mask = BIT(0),
1312 .halt_reg = 0x3188,
1314 .enable_reg = 0x3188,
1315 .enable_mask = BIT(0),
1327 .halt_reg = 0x3184,
1329 .enable_reg = 0x3184,
1330 .enable_mask = BIT(0),
1341 .halt_reg = 0x3194,
1343 .enable_reg = 0x3194,
1344 .enable_mask = BIT(0),
1355 .halt_reg = 0x31b4,
1357 .enable_reg = 0x31b4,
1358 .enable_mask = BIT(0),
1369 .halt_reg = 0x31a4,
1371 .enable_reg = 0x31a4,
1372 .enable_mask = BIT(0),
1383 .halt_reg = 0x31e8,
1385 .enable_reg = 0x31e8,
1386 .enable_mask = BIT(0),
1398 .halt_reg = 0x31e4,
1400 .enable_reg = 0x31e4,
1401 .enable_mask = BIT(0),
1412 .halt_reg = 0x31f4,
1414 .enable_reg = 0x31f4,
1415 .enable_mask = BIT(0),
1426 .halt_reg = 0x3214,
1428 .enable_reg = 0x3214,
1429 .enable_mask = BIT(0),
1440 .halt_reg = 0x3204,
1442 .enable_reg = 0x3204,
1443 .enable_mask = BIT(0),
1454 .halt_reg = 0x3704,
1456 .enable_reg = 0x3704,
1457 .enable_mask = BIT(0),
1468 .halt_reg = 0x3714,
1470 .enable_reg = 0x3714,
1471 .enable_mask = BIT(0),
1482 .halt_reg = 0x3444,
1484 .enable_reg = 0x3444,
1485 .enable_mask = BIT(0),
1496 .halt_reg = 0x3474,
1498 .enable_reg = 0x3474,
1499 .enable_mask = BIT(0),
1510 .halt_reg = 0x3224,
1512 .enable_reg = 0x3224,
1513 .enable_mask = BIT(0),
1525 .halt_reg = 0x35c0,
1527 .enable_reg = 0x35c0,
1528 .enable_mask = BIT(0),
1539 .halt_reg = 0x35a8,
1541 .enable_reg = 0x35a8,
1542 .enable_mask = BIT(0),
1553 .halt_reg = 0x35ac,
1555 .enable_reg = 0x35ac,
1556 .enable_mask = BIT(0),
1567 .halt_reg = 0x35b0,
1569 .enable_reg = 0x35b0,
1570 .enable_mask = BIT(0),
1581 .halt_reg = 0x35b4,
1583 .enable_reg = 0x35b4,
1584 .enable_mask = BIT(0),
1596 .halt_reg = 0x35b8,
1598 .enable_reg = 0x35b8,
1599 .enable_mask = BIT(0),
1610 .halt_reg = 0x3384,
1612 .enable_reg = 0x3384,
1613 .enable_mask = BIT(0),
1624 .halt_reg = 0x33b4,
1626 .enable_reg = 0x33b4,
1627 .enable_mask = BIT(0),
1638 .halt_reg = 0x33e4,
1640 .enable_reg = 0x33e4,
1641 .enable_mask = BIT(0),
1652 .halt_reg = 0x3414,
1654 .enable_reg = 0x3414,
1655 .enable_mask = BIT(0),
1666 .halt_reg = 0x3494,
1668 .enable_reg = 0x3494,
1669 .enable_mask = BIT(0),
1681 .halt_reg = 0x3024,
1683 .enable_reg = 0x3024,
1684 .enable_mask = BIT(0),
1695 .halt_reg = 0x3054,
1697 .enable_reg = 0x3054,
1698 .enable_mask = BIT(0),
1709 .halt_reg = 0x3084,
1711 .enable_reg = 0x3084,
1712 .enable_mask = BIT(0),
1723 .halt_reg = 0x3484,
1725 .enable_reg = 0x3484,
1726 .enable_mask = BIT(0),
1738 .halt_reg = 0x36a8,
1740 .enable_reg = 0x36a8,
1741 .enable_mask = BIT(0),
1752 .halt_reg = 0x36ac,
1754 .enable_reg = 0x36ac,
1755 .enable_mask = BIT(0),
1766 .halt_reg = 0x36b8,
1768 .enable_reg = 0x36b8,
1769 .enable_mask = BIT(0),
1781 .halt_reg = 0x36bc,
1783 .enable_reg = 0x36bc,
1784 .enable_mask = BIT(0),
1795 .halt_reg = 0x3b74,
1797 .enable_reg = 0x3b74,
1798 .enable_mask = BIT(0),
1809 .halt_reg = 0x3b70,
1811 .enable_reg = 0x3b70,
1812 .enable_mask = BIT(0),
1823 .halt_reg = 0x3b68,
1825 .enable_reg = 0x3b68,
1826 .enable_mask = BIT(0),
1837 .halt_reg = 0x3b6c,
1839 .enable_reg = 0x3b6c,
1840 .enable_mask = BIT(0),
1851 .halt_reg = 0x2308,
1854 .enable_reg = 0x2308,
1855 .enable_mask = BIT(0),
1867 .halt_reg = 0x2310,
1869 .enable_reg = 0x2310,
1870 .enable_mask = BIT(0),
1882 .halt_reg = 0x233c,
1884 .enable_reg = 0x233c,
1885 .enable_mask = BIT(0),
1897 .halt_reg = 0x2340,
1899 .enable_reg = 0x2340,
1900 .enable_mask = BIT(0),
1912 .halt_reg = 0x2344,
1914 .enable_reg = 0x2344,
1915 .enable_mask = BIT(0),
1927 .halt_reg = 0x2348,
1929 .enable_reg = 0x2348,
1930 .enable_mask = BIT(0),
1942 .halt_reg = 0x2324,
1944 .enable_reg = 0x2324,
1945 .enable_mask = BIT(0),
1957 .halt_reg = 0x230c,
1959 .enable_reg = 0x230c,
1960 .enable_mask = BIT(0),
1972 .halt_reg = 0x2338,
1974 .enable_reg = 0x2338,
1975 .enable_mask = BIT(0),
1987 .halt_reg = 0x231c,
1989 .enable_reg = 0x231c,
1990 .enable_mask = BIT(0),
2002 .halt_reg = 0x2314,
2004 .enable_reg = 0x2314,
2005 .enable_mask = BIT(0),
2017 .halt_reg = 0x2318,
2019 .enable_reg = 0x2318,
2020 .enable_mask = BIT(0),
2032 .halt_reg = 0x2328,
2034 .enable_reg = 0x2328,
2035 .enable_mask = BIT(0),
2047 .halt_reg = 0x502c,
2049 .enable_reg = 0x502c,
2050 .enable_mask = BIT(0),
2062 .halt_reg = 0x506c,
2064 .enable_reg = 0x506c,
2065 .enable_mask = BIT(0),
2078 .halt_reg = 0x5064,
2080 .enable_reg = 0x5064,
2081 .enable_mask = BIT(0),
2093 .halt_reg = 0x4058,
2095 .enable_reg = 0x4058,
2096 .enable_mask = BIT(0),
2108 .halt_reg = 0x4028,
2110 .enable_reg = 0x4028,
2111 .enable_mask = BIT(0),
2126 .halt_reg = 0x40b0,
2128 .enable_reg = 0x40b0,
2129 .enable_mask = BIT(0),
2141 .halt_reg = 0x403c,
2143 .enable_reg = 0x403c,
2144 .enable_mask = BIT(0),
2156 .halt_reg = 0x1030,
2158 .enable_reg = 0x1030,
2159 .enable_mask = BIT(0),
2171 .halt_reg = 0x1034,
2173 .enable_reg = 0x1034,
2174 .enable_mask = BIT(0),
2185 .halt_reg = 0x1038,
2187 .enable_reg = 0x1038,
2188 .enable_mask = BIT(0),
2200 .halt_reg = 0x1028,
2202 .enable_reg = 0x1028,
2203 .enable_mask = BIT(0),
2215 .halt_reg = 0x1048,
2217 .enable_reg = 0x1048,
2218 .enable_mask = BIT(0),
2230 .halt_reg = 0x104c,
2232 .enable_reg = 0x104c,
2233 .enable_mask = BIT(0),
2245 .halt_reg = 0x1054,
2247 .enable_reg = 0x1054,
2248 .enable_mask = BIT(0),
2260 .gdscr = 0x1024,
2261 .cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2270 .gdscr = 0x1040,
2271 .cxcs = (unsigned int []){ 0x1048 },
2281 .gdscr = 0x1044,
2282 .cxcs = (unsigned int []){ 0x104c },
2292 .gdscr = 0x1050,
2293 .cxcs = (unsigned int []){ 0x1054 },
2303 .gdscr = 0x2304,
2304 .cxcs = (unsigned int []){ 0x2310, 0x231c },
2313 .gdscr = 0x34a0,
2314 .cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2323 .gdscr = 0x35a4,
2324 .cxcs = (unsigned int []){ 0x35a8 },
2334 .gdscr = 0x36a4,
2335 .cxcs = (unsigned int []){ 0x36bc },
2345 .gdscr = 0x36d4,
2346 .cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2356 .gdscr = 0x3b64,
2357 .cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2365 .gdscr = 0x4034,
2374 .gdscr = 0x4024,
2375 .cxcs = (unsigned int []){ 0x4028 },
2532 [CAMSS_MICRO_BCR] = { 0x3490 },
2539 .max_register = 0x5200,