Lines Matching +full:0 +full:x3150
46 { P_XO, 0 },
60 { P_XO, 0 },
78 { P_XO, 0 },
94 { P_XO, 0 },
110 { P_XO, 0 },
128 { P_XO, 0 },
146 { P_XO, 0 },
164 .l_reg = 0x0004,
165 .m_reg = 0x0008,
166 .n_reg = 0x000c,
167 .config_reg = 0x0014,
168 .mode_reg = 0x0000,
169 .status_reg = 0x001c,
180 .enable_reg = 0x0100,
181 .enable_mask = BIT(0),
191 .l_reg = 0x0044,
192 .m_reg = 0x0048,
193 .n_reg = 0x004c,
194 .config_reg = 0x0050,
195 .mode_reg = 0x0040,
196 .status_reg = 0x005c,
207 .enable_reg = 0x0100,
218 .l_reg = 0x4104,
219 .m_reg = 0x4108,
220 .n_reg = 0x410c,
221 .config_reg = 0x4110,
222 .mode_reg = 0x4100,
223 .status_reg = 0x411c,
233 .l_reg = 0x0084,
234 .m_reg = 0x0088,
235 .n_reg = 0x008c,
236 .config_reg = 0x0090,
237 .mode_reg = 0x0080,
238 .status_reg = 0x009c,
249 .cmd_rcgr = 0x5000,
261 F(19200000, P_XO, 1, 0, 0),
262 F(37500000, P_GPLL0, 16, 0, 0),
263 F(50000000, P_GPLL0, 12, 0, 0),
264 F(75000000, P_GPLL0, 8, 0, 0),
265 F(100000000, P_GPLL0, 6, 0, 0),
266 F(150000000, P_GPLL0, 4, 0, 0),
267 F(200000000, P_MMPLL0, 4, 0, 0),
268 F(266666666, P_MMPLL0, 3, 0, 0),
273 F( 19200000, P_XO, 1, 0, 0),
274 F( 37500000, P_GPLL0, 16, 0, 0),
275 F( 50000000, P_GPLL0, 12, 0, 0),
276 F( 75000000, P_GPLL0, 8, 0, 0),
277 F(100000000, P_GPLL0, 6, 0, 0),
278 F(150000000, P_GPLL0, 4, 0, 0),
279 F(291750000, P_MMPLL1, 4, 0, 0),
280 F(400000000, P_MMPLL0, 2, 0, 0),
281 F(466800000, P_MMPLL1, 2.5, 0, 0),
285 .cmd_rcgr = 0x5040,
298 F( 19200000, P_XO, 1, 0, 0),
299 F( 37500000, P_GPLL0, 16, 0, 0),
300 F( 50000000, P_GPLL0, 12, 0, 0),
301 F( 75000000, P_GPLL0, 8, 0, 0),
302 F(100000000, P_GPLL0, 6, 0, 0),
303 F(150000000, P_GPLL0, 4, 0, 0),
304 F(291750000, P_MMPLL1, 4, 0, 0),
305 F(400000000, P_MMPLL0, 2, 0, 0),
309 .cmd_rcgr = 0x5090,
322 F(100000000, P_GPLL0, 6, 0, 0),
323 F(200000000, P_MMPLL0, 4, 0, 0),
328 .cmd_rcgr = 0x3090,
341 .cmd_rcgr = 0x3100,
354 .cmd_rcgr = 0x3160,
367 .cmd_rcgr = 0x31c0,
380 F(37500000, P_GPLL0, 16, 0, 0),
381 F(50000000, P_GPLL0, 12, 0, 0),
382 F(60000000, P_GPLL0, 10, 0, 0),
383 F(80000000, P_GPLL0, 7.5, 0, 0),
384 F(100000000, P_GPLL0, 6, 0, 0),
385 F(109090000, P_GPLL0, 5.5, 0, 0),
386 F(133330000, P_GPLL0, 4.5, 0, 0),
387 F(150000000, P_GPLL0, 4, 0, 0),
388 F(200000000, P_GPLL0, 3, 0, 0),
389 F(228570000, P_MMPLL0, 3.5, 0, 0),
390 F(266670000, P_MMPLL0, 3, 0, 0),
391 F(320000000, P_MMPLL0, 2.5, 0, 0),
392 F(400000000, P_MMPLL0, 2, 0, 0),
397 F(37500000, P_GPLL0, 16, 0, 0),
398 F(50000000, P_GPLL0, 12, 0, 0),
399 F(60000000, P_GPLL0, 10, 0, 0),
400 F(80000000, P_GPLL0, 7.5, 0, 0),
401 F(100000000, P_GPLL0, 6, 0, 0),
402 F(109090000, P_GPLL0, 5.5, 0, 0),
403 F(133330000, P_GPLL0, 4.5, 0, 0),
404 F(200000000, P_GPLL0, 3, 0, 0),
405 F(228570000, P_MMPLL0, 3.5, 0, 0),
406 F(266670000, P_MMPLL0, 3, 0, 0),
407 F(320000000, P_MMPLL0, 2.5, 0, 0),
408 F(400000000, P_MMPLL0, 2, 0, 0),
409 F(465000000, P_MMPLL3, 2, 0, 0),
414 .cmd_rcgr = 0x3600,
427 .cmd_rcgr = 0x3620,
440 F(37500000, P_GPLL0, 16, 0, 0),
441 F(60000000, P_GPLL0, 10, 0, 0),
442 F(75000000, P_GPLL0, 8, 0, 0),
443 F(92310000, P_GPLL0, 6.5, 0, 0),
444 F(100000000, P_GPLL0, 6, 0, 0),
445 F(133330000, P_MMPLL0, 6, 0, 0),
446 F(177780000, P_MMPLL0, 4.5, 0, 0),
447 F(200000000, P_MMPLL0, 4, 0, 0),
452 F(37500000, P_GPLL0, 16, 0, 0),
453 F(60000000, P_GPLL0, 10, 0, 0),
454 F(75000000, P_GPLL0, 8, 0, 0),
455 F(85710000, P_GPLL0, 7, 0, 0),
456 F(100000000, P_GPLL0, 6, 0, 0),
457 F(133330000, P_MMPLL0, 6, 0, 0),
458 F(160000000, P_MMPLL0, 5, 0, 0),
459 F(200000000, P_MMPLL0, 4, 0, 0),
460 F(228570000, P_MMPLL0, 3.5, 0, 0),
461 F(240000000, P_GPLL0, 2.5, 0, 0),
462 F(266670000, P_MMPLL0, 3, 0, 0),
463 F(320000000, P_MMPLL0, 2.5, 0, 0),
468 .cmd_rcgr = 0x2040,
481 F(75000000, P_GPLL0, 8, 0, 0),
482 F(133330000, P_GPLL0, 4.5, 0, 0),
483 F(200000000, P_GPLL0, 3, 0, 0),
484 F(228570000, P_MMPLL0, 3.5, 0, 0),
485 F(266670000, P_MMPLL0, 3, 0, 0),
486 F(320000000, P_MMPLL0, 2.5, 0, 0),
491 .cmd_rcgr = 0x3500,
504 .cmd_rcgr = 0x3520,
517 .cmd_rcgr = 0x3540,
530 .cmd_rcgr = 0x2000,
544 .cmd_rcgr = 0x2020,
558 F(66700000, P_GPLL0, 9, 0, 0),
559 F(100000000, P_GPLL0, 6, 0, 0),
560 F(133330000, P_MMPLL0, 6, 0, 0),
561 F(160000000, P_MMPLL0, 5, 0, 0),
566 F(50000000, P_GPLL0, 12, 0, 0),
567 F(100000000, P_GPLL0, 6, 0, 0),
568 F(133330000, P_MMPLL0, 6, 0, 0),
569 F(200000000, P_MMPLL0, 4, 0, 0),
570 F(266670000, P_MMPLL0, 3, 0, 0),
571 F(465000000, P_MMPLL3, 2, 0, 0),
576 .cmd_rcgr = 0x1000,
590 F(19200000, P_XO, 1, 0, 0),
595 .cmd_rcgr = 0x3300,
618 .cmd_rcgr = 0x3420,
632 .cmd_rcgr = 0x3450,
646 F(19200000, P_XO, 1, 0, 0),
648 F(66670000, P_GPLL0, 9, 0, 0),
653 F(4800000, P_XO, 4, 0, 0),
656 F(9600000, P_XO, 2, 0, 0),
658 F(19200000, P_XO, 1, 0, 0),
661 F(48000000, P_GPLL0, 12.5, 0, 0),
662 F(64000000, P_MMPLL0, 12.5, 0, 0),
663 F(66670000, P_GPLL0, 9, 0, 0),
668 .cmd_rcgr = 0x3360,
681 .cmd_rcgr = 0x3390,
694 .cmd_rcgr = 0x33c0,
707 .cmd_rcgr = 0x33f0,
720 F(100000000, P_GPLL0, 6, 0, 0),
721 F(200000000, P_MMPLL0, 4, 0, 0),
726 .cmd_rcgr = 0x3000,
739 .cmd_rcgr = 0x3030,
752 .cmd_rcgr = 0x3060,
765 F(133330000, P_GPLL0, 4.5, 0, 0),
766 F(150000000, P_GPLL0, 4, 0, 0),
767 F(266670000, P_MMPLL0, 3, 0, 0),
768 F(320000000, P_MMPLL0, 2.5, 0, 0),
769 F(400000000, P_MMPLL0, 2, 0, 0),
774 F(133330000, P_GPLL0, 4.5, 0, 0),
775 F(266670000, P_MMPLL0, 3, 0, 0),
776 F(320000000, P_MMPLL0, 2.5, 0, 0),
777 F(400000000, P_MMPLL0, 2, 0, 0),
778 F(465000000, P_MMPLL3, 2, 0, 0),
783 .cmd_rcgr = 0x3640,
801 .cmd_rcgr = 0x2120,
815 .cmd_rcgr = 0x2140,
829 F(19200000, P_XO, 1, 0, 0),
834 .cmd_rcgr = 0x20e0,
847 F(135000000, P_EDPLINK, 2, 0, 0),
848 F(270000000, P_EDPLINK, 11, 0, 0),
853 .cmd_rcgr = 0x20c0,
872 .cmd_rcgr = 0x20a0,
886 F(19200000, P_XO, 1, 0, 0),
891 .cmd_rcgr = 0x2160,
904 .cmd_rcgr = 0x2180,
922 .cmd_rcgr = 0x2060,
936 F(19200000, P_XO, 1, 0, 0),
941 .cmd_rcgr = 0x2100,
954 F(19200000, P_XO, 1, 0, 0),
959 .cmd_rcgr = 0x2080,
972 .halt_reg = 0x3348,
974 .enable_reg = 0x3348,
975 .enable_mask = BIT(0),
988 .halt_reg = 0x3344,
990 .enable_reg = 0x3344,
991 .enable_mask = BIT(0),
1005 .halt_reg = 0x30bc,
1007 .enable_reg = 0x30bc,
1008 .enable_mask = BIT(0),
1021 .halt_reg = 0x30b4,
1023 .enable_reg = 0x30b4,
1024 .enable_mask = BIT(0),
1038 .halt_reg = 0x30c4,
1040 .enable_reg = 0x30c4,
1041 .enable_mask = BIT(0),
1055 .halt_reg = 0x30e4,
1057 .enable_reg = 0x30e4,
1058 .enable_mask = BIT(0),
1072 .halt_reg = 0x30d4,
1074 .enable_reg = 0x30d4,
1075 .enable_mask = BIT(0),
1089 .halt_reg = 0x3128,
1091 .enable_reg = 0x3128,
1092 .enable_mask = BIT(0),
1105 .halt_reg = 0x3124,
1107 .enable_reg = 0x3124,
1108 .enable_mask = BIT(0),
1122 .halt_reg = 0x3134,
1124 .enable_reg = 0x3134,
1125 .enable_mask = BIT(0),
1139 .halt_reg = 0x3154,
1141 .enable_reg = 0x3154,
1142 .enable_mask = BIT(0),
1156 .halt_reg = 0x3144,
1158 .enable_reg = 0x3144,
1159 .enable_mask = BIT(0),
1173 .halt_reg = 0x3188,
1175 .enable_reg = 0x3188,
1176 .enable_mask = BIT(0),
1189 .halt_reg = 0x3184,
1191 .enable_reg = 0x3184,
1192 .enable_mask = BIT(0),
1206 .halt_reg = 0x3194,
1208 .enable_reg = 0x3194,
1209 .enable_mask = BIT(0),
1223 .halt_reg = 0x31b4,
1225 .enable_reg = 0x31b4,
1226 .enable_mask = BIT(0),
1240 .halt_reg = 0x31a4,
1242 .enable_reg = 0x31a4,
1243 .enable_mask = BIT(0),
1257 .halt_reg = 0x31e8,
1259 .enable_reg = 0x31e8,
1260 .enable_mask = BIT(0),
1273 .halt_reg = 0x31e4,
1275 .enable_reg = 0x31e4,
1276 .enable_mask = BIT(0),
1290 .halt_reg = 0x31f4,
1292 .enable_reg = 0x31f4,
1293 .enable_mask = BIT(0),
1307 .halt_reg = 0x3214,
1309 .enable_reg = 0x3214,
1310 .enable_mask = BIT(0),
1324 .halt_reg = 0x3204,
1326 .enable_reg = 0x3204,
1327 .enable_mask = BIT(0),
1341 .halt_reg = 0x3704,
1343 .enable_reg = 0x3704,
1344 .enable_mask = BIT(0),
1358 .halt_reg = 0x3714,
1360 .enable_reg = 0x3714,
1361 .enable_mask = BIT(0),
1375 .halt_reg = 0x3444,
1377 .enable_reg = 0x3444,
1378 .enable_mask = BIT(0),
1392 .halt_reg = 0x3474,
1394 .enable_reg = 0x3474,
1395 .enable_mask = BIT(0),
1409 .halt_reg = 0x3224,
1411 .enable_reg = 0x3224,
1412 .enable_mask = BIT(0),
1425 .halt_reg = 0x35a8,
1427 .enable_reg = 0x35a8,
1428 .enable_mask = BIT(0),
1442 .halt_reg = 0x35ac,
1444 .enable_reg = 0x35ac,
1445 .enable_mask = BIT(0),
1459 .halt_reg = 0x35b0,
1461 .enable_reg = 0x35b0,
1462 .enable_mask = BIT(0),
1476 .halt_reg = 0x35b4,
1478 .enable_reg = 0x35b4,
1479 .enable_mask = BIT(0),
1492 .halt_reg = 0x35b8,
1494 .enable_reg = 0x35b8,
1495 .enable_mask = BIT(0),
1508 .halt_reg = 0x35bc,
1510 .enable_reg = 0x35bc,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0x3384,
1527 .enable_reg = 0x3384,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0x33b4,
1544 .enable_reg = 0x33b4,
1545 .enable_mask = BIT(0),
1559 .halt_reg = 0x33e4,
1561 .enable_reg = 0x33e4,
1562 .enable_mask = BIT(0),
1576 .halt_reg = 0x3414,
1578 .enable_reg = 0x3414,
1579 .enable_mask = BIT(0),
1593 .halt_reg = 0x3494,
1595 .enable_reg = 0x3494,
1596 .enable_mask = BIT(0),
1609 .halt_reg = 0x3024,
1611 .enable_reg = 0x3024,
1612 .enable_mask = BIT(0),
1626 .halt_reg = 0x3054,
1628 .enable_reg = 0x3054,
1629 .enable_mask = BIT(0),
1643 .halt_reg = 0x3084,
1645 .enable_reg = 0x3084,
1646 .enable_mask = BIT(0),
1660 .halt_reg = 0x3484,
1662 .enable_reg = 0x3484,
1663 .enable_mask = BIT(0),
1676 .halt_reg = 0x36b4,
1678 .enable_reg = 0x36b4,
1679 .enable_mask = BIT(0),
1692 .halt_reg = 0x36b0,
1694 .enable_reg = 0x36b0,
1695 .enable_mask = BIT(0),
1709 .halt_reg = 0x36a8,
1711 .enable_reg = 0x36a8,
1712 .enable_mask = BIT(0),
1726 .halt_reg = 0x36ac,
1728 .enable_reg = 0x36ac,
1729 .enable_mask = BIT(0),
1743 .halt_reg = 0x36b8,
1745 .enable_reg = 0x36b8,
1746 .enable_mask = BIT(0),
1759 .halt_reg = 0x36bc,
1761 .enable_reg = 0x36bc,
1762 .enable_mask = BIT(0),
1775 .halt_reg = 0x36c0,
1777 .enable_reg = 0x36c0,
1778 .enable_mask = BIT(0),
1792 .halt_reg = 0x2308,
1794 .enable_reg = 0x2308,
1795 .enable_mask = BIT(0),
1808 .halt_reg = 0x2310,
1810 .enable_reg = 0x2310,
1811 .enable_mask = BIT(0),
1825 .halt_reg = 0x233c,
1827 .enable_reg = 0x233c,
1828 .enable_mask = BIT(0),
1842 .halt_reg = 0x2340,
1844 .enable_reg = 0x2340,
1845 .enable_mask = BIT(0),
1859 .halt_reg = 0x2334,
1861 .enable_reg = 0x2334,
1862 .enable_mask = BIT(0),
1876 .halt_reg = 0x2330,
1878 .enable_reg = 0x2330,
1879 .enable_mask = BIT(0),
1893 .halt_reg = 0x232c,
1895 .enable_reg = 0x232c,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x2344,
1912 .enable_reg = 0x2344,
1913 .enable_mask = BIT(0),
1927 .halt_reg = 0x2348,
1929 .enable_reg = 0x2348,
1930 .enable_mask = BIT(0),
1944 .halt_reg = 0x2324,
1946 .enable_reg = 0x2324,
1947 .enable_mask = BIT(0),
1961 .halt_reg = 0x230c,
1963 .enable_reg = 0x230c,
1964 .enable_mask = BIT(0),
1977 .halt_reg = 0x2338,
1979 .enable_reg = 0x2338,
1980 .enable_mask = BIT(0),
1994 .halt_reg = 0x231c,
1996 .enable_reg = 0x231c,
1997 .enable_mask = BIT(0),
2011 .halt_reg = 0x2320,
2013 .enable_reg = 0x2320,
2014 .enable_mask = BIT(0),
2028 .halt_reg = 0x2314,
2030 .enable_reg = 0x2314,
2031 .enable_mask = BIT(0),
2045 .halt_reg = 0x2318,
2047 .enable_reg = 0x2318,
2048 .enable_mask = BIT(0),
2062 .halt_reg = 0x2328,
2064 .enable_reg = 0x2328,
2065 .enable_mask = BIT(0),
2079 .halt_reg = 0x502c,
2081 .enable_reg = 0x502c,
2082 .enable_mask = BIT(0),
2095 .halt_reg = 0x5024,
2097 .enable_reg = 0x5024,
2098 .enable_mask = BIT(0),
2112 .halt_reg = 0x5028,
2114 .enable_reg = 0x5028,
2115 .enable_mask = BIT(0),
2129 .halt_reg = 0x506c,
2131 .enable_reg = 0x506c,
2132 .enable_mask = BIT(0),
2146 .halt_reg = 0x5064,
2148 .enable_reg = 0x5064,
2149 .enable_mask = BIT(0),
2163 .halt_reg = 0x405c,
2165 .enable_reg = 0x405c,
2166 .enable_mask = BIT(0),
2179 .halt_reg = 0x4058,
2181 .enable_reg = 0x4058,
2182 .enable_mask = BIT(0),
2196 .halt_reg = 0x402c,
2198 .enable_reg = 0x402c,
2199 .enable_mask = BIT(0),
2213 .halt_reg = 0x50b4,
2215 .enable_reg = 0x50b4,
2216 .enable_mask = BIT(0),
2230 .halt_reg = 0x4028,
2232 .enable_reg = 0x4028,
2233 .enable_mask = BIT(0),
2247 .halt_reg = 0x403c,
2249 .enable_reg = 0x403c,
2250 .enable_mask = BIT(0),
2263 .halt_reg = 0x4038,
2265 .enable_reg = 0x4038,
2266 .enable_mask = BIT(0),
2279 .halt_reg = 0x1030,
2281 .enable_reg = 0x1030,
2282 .enable_mask = BIT(0),
2295 .halt_reg = 0x1034,
2297 .enable_reg = 0x1034,
2298 .enable_mask = BIT(0),
2311 .halt_reg = 0x1038,
2313 .enable_reg = 0x1038,
2314 .enable_mask = BIT(0),
2328 .halt_reg = 0x1028,
2330 .enable_reg = 0x1028,
2331 .enable_mask = BIT(0),
2348 .vco_val = 0x0,
2349 .vco_mask = 0x3 << 20,
2350 .pre_div_val = 0x0,
2351 .pre_div_mask = 0x7 << 12,
2352 .post_div_val = 0x0,
2353 .post_div_mask = 0x3 << 8,
2355 .main_output_mask = BIT(0),
2362 .vco_val = 0x0,
2363 .vco_mask = 0x3 << 20,
2364 .pre_div_val = 0x0,
2365 .pre_div_mask = 0x7 << 12,
2366 .post_div_val = 0x0,
2367 .post_div_mask = 0x3 << 8,
2369 .main_output_mask = BIT(0),
2374 .gdscr = 0x1024,
2375 .cxcs = (unsigned int []){ 0x1028 },
2386 .gdscr = 0x2304,
2387 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2396 .gdscr = 0x35a4,
2397 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2406 .gdscr = 0x36a4,
2407 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2416 .gdscr = 0x4024,
2417 .cxcs = (unsigned int []){ 0x4028 },
2426 .gdscr = 0x4034,
2513 [SPDM_RESET] = { 0x0200 },
2514 [SPDM_RM_RESET] = { 0x0300 },
2515 [VENUS0_RESET] = { 0x1020 },
2516 [MDSS_RESET] = { 0x2300 },
2530 .max_register = 0x5104,
2673 [SPDM_RESET] = { 0x0200 },
2674 [SPDM_RM_RESET] = { 0x0300 },
2675 [VENUS0_RESET] = { 0x1020 },
2676 [MDSS_RESET] = { 0x2300 },
2677 [CAMSS_PHY0_RESET] = { 0x3020 },
2678 [CAMSS_PHY1_RESET] = { 0x3050 },
2679 [CAMSS_PHY2_RESET] = { 0x3080 },
2680 [CAMSS_CSI0_RESET] = { 0x30b0 },
2681 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2682 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2683 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2684 [CAMSS_CSI1_RESET] = { 0x3120 },
2685 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2686 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2687 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2688 [CAMSS_CSI2_RESET] = { 0x3180 },
2689 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2690 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2691 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2692 [CAMSS_CSI3_RESET] = { 0x31e0 },
2693 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2694 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2695 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2696 [CAMSS_ISPIF_RESET] = { 0x3220 },
2697 [CAMSS_CCI_RESET] = { 0x3340 },
2698 [CAMSS_MCLK0_RESET] = { 0x3380 },
2699 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2700 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2701 [CAMSS_MCLK3_RESET] = { 0x3410 },
2702 [CAMSS_GP0_RESET] = { 0x3440 },
2703 [CAMSS_GP1_RESET] = { 0x3470 },
2704 [CAMSS_TOP_RESET] = { 0x3480 },
2705 [CAMSS_MICRO_RESET] = { 0x3490 },
2706 [CAMSS_JPEG_RESET] = { 0x35a0 },
2707 [CAMSS_VFE_RESET] = { 0x36a0 },
2708 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2709 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2710 [OXILI_RESET] = { 0x4020 },
2711 [OXILICX_RESET] = { 0x4030 },
2712 [OCMEMCX_RESET] = { 0x4050 },
2713 [MMSS_RBCRP_RESET] = { 0x4080 },
2714 [MMSSNOCAHB_RESET] = { 0x5020 },
2715 [MMSSNOCAXI_RESET] = { 0x5060 },
2716 [OCMEMNOC_RESET] = { 0x50b0 },
2732 .max_register = 0x5104,