Lines Matching +full:0 +full:x3150
44 { P_XO, 0 },
58 { P_XO, 0 },
76 { P_XO, 0 },
92 { P_XO, 0 },
108 { P_XO, 0 },
126 { P_XO, 0 },
144 { P_XO, 0 },
162 { P_XO, 0 },
178 { P_XO, 0 },
196 { P_XO, 0 },
216 .l_reg = 0x0004,
217 .m_reg = 0x0008,
218 .n_reg = 0x000c,
219 .config_reg = 0x0014,
220 .mode_reg = 0x0000,
221 .status_reg = 0x001c,
232 .enable_reg = 0x0100,
233 .enable_mask = BIT(0),
243 .l_reg = 0x0044,
244 .m_reg = 0x0048,
245 .n_reg = 0x004c,
246 .config_reg = 0x0050,
247 .mode_reg = 0x0040,
248 .status_reg = 0x005c,
259 .enable_reg = 0x0100,
270 .l_reg = 0x4104,
271 .m_reg = 0x4108,
272 .n_reg = 0x410c,
273 .config_reg = 0x4110,
274 .mode_reg = 0x4100,
275 .status_reg = 0x411c,
285 .l_reg = 0x0084,
286 .m_reg = 0x0088,
287 .n_reg = 0x008c,
288 .config_reg = 0x0090,
289 .mode_reg = 0x0080,
290 .status_reg = 0x009c,
301 .l_reg = 0x00a4,
302 .m_reg = 0x00a8,
303 .n_reg = 0x00ac,
304 .config_reg = 0x00b0,
305 .mode_reg = 0x0080,
306 .status_reg = 0x00bc,
316 .cmd_rcgr = 0x5000,
328 F(19200000, P_XO, 1, 0, 0),
329 F(37500000, P_GPLL0, 16, 0, 0),
330 F(50000000, P_GPLL0, 12, 0, 0),
331 F(75000000, P_GPLL0, 8, 0, 0),
332 F(100000000, P_GPLL0, 6, 0, 0),
333 F(150000000, P_GPLL0, 4, 0, 0),
334 F(333430000, P_MMPLL1, 3.5, 0, 0),
335 F(400000000, P_MMPLL0, 2, 0, 0),
336 F(466800000, P_MMPLL1, 2.5, 0, 0),
340 .cmd_rcgr = 0x5040,
353 F(19200000, P_XO, 1, 0, 0),
354 F(37500000, P_GPLL0, 16, 0, 0),
355 F(50000000, P_GPLL0, 12, 0, 0),
356 F(75000000, P_GPLL0, 8, 0, 0),
357 F(109090000, P_GPLL0, 5.5, 0, 0),
358 F(150000000, P_GPLL0, 4, 0, 0),
359 F(228570000, P_MMPLL0, 3.5, 0, 0),
360 F(320000000, P_MMPLL0, 2.5, 0, 0),
364 .cmd_rcgr = 0x5090,
377 F(100000000, P_GPLL0, 6, 0, 0),
378 F(200000000, P_MMPLL0, 4, 0, 0),
383 .cmd_rcgr = 0x3090,
396 .cmd_rcgr = 0x3100,
409 .cmd_rcgr = 0x3160,
422 .cmd_rcgr = 0x31c0,
435 F(37500000, P_GPLL0, 16, 0, 0),
436 F(50000000, P_GPLL0, 12, 0, 0),
437 F(60000000, P_GPLL0, 10, 0, 0),
438 F(80000000, P_GPLL0, 7.5, 0, 0),
439 F(100000000, P_GPLL0, 6, 0, 0),
440 F(109090000, P_GPLL0, 5.5, 0, 0),
441 F(133330000, P_GPLL0, 4.5, 0, 0),
442 F(200000000, P_GPLL0, 3, 0, 0),
443 F(228570000, P_MMPLL0, 3.5, 0, 0),
444 F(266670000, P_MMPLL0, 3, 0, 0),
445 F(320000000, P_MMPLL0, 2.5, 0, 0),
446 F(465000000, P_MMPLL4, 2, 0, 0),
447 F(600000000, P_GPLL0, 1, 0, 0),
452 .cmd_rcgr = 0x3600,
465 .cmd_rcgr = 0x3620,
478 F(37500000, P_GPLL0, 16, 0, 0),
479 F(60000000, P_GPLL0, 10, 0, 0),
480 F(75000000, P_GPLL0, 8, 0, 0),
481 F(85710000, P_GPLL0, 7, 0, 0),
482 F(100000000, P_GPLL0, 6, 0, 0),
483 F(150000000, P_GPLL0, 4, 0, 0),
484 F(160000000, P_MMPLL0, 5, 0, 0),
485 F(200000000, P_MMPLL0, 4, 0, 0),
486 F(228570000, P_MMPLL0, 3.5, 0, 0),
487 F(300000000, P_GPLL0, 2, 0, 0),
488 F(320000000, P_MMPLL0, 2.5, 0, 0),
493 .cmd_rcgr = 0x2040,
506 .cmd_rcgr = 0x4000,
518 F(75000000, P_GPLL0, 8, 0, 0),
519 F(133330000, P_GPLL0, 4.5, 0, 0),
520 F(200000000, P_GPLL0, 3, 0, 0),
521 F(228570000, P_MMPLL0, 3.5, 0, 0),
522 F(266670000, P_MMPLL0, 3, 0, 0),
523 F(320000000, P_MMPLL0, 2.5, 0, 0),
528 .cmd_rcgr = 0x3500,
541 .cmd_rcgr = 0x3520,
554 .cmd_rcgr = 0x3540,
567 .cmd_rcgr = 0x2000,
581 .cmd_rcgr = 0x2020,
595 F(50000000, P_GPLL0, 12, 0, 0),
596 F(100000000, P_GPLL0, 6, 0, 0),
597 F(133330000, P_GPLL0, 4.5, 0, 0),
598 F(200000000, P_MMPLL0, 4, 0, 0),
599 F(266670000, P_MMPLL0, 3, 0, 0),
600 F(465000000, P_MMPLL3, 2, 0, 0),
605 .cmd_rcgr = 0x1000,
619 F(150000000, P_GPLL0, 4, 0, 0),
620 F(320000000, P_MMPLL0, 2.5, 0, 0),
625 .cmd_rcgr = 0x2430,
638 F(19200000, P_XO, 1, 0, 0),
643 .cmd_rcgr = 0x3300,
667 .cmd_rcgr = 0x3420,
681 .cmd_rcgr = 0x3450,
695 F(4800000, P_XO, 4, 0, 0),
698 F(9600000, P_XO, 2, 0, 0),
700 F(19200000, P_XO, 1, 0, 0),
703 F(48000000, P_GPLL0, 12.5, 0, 0),
704 F(64000000, P_MMPLL0, 12.5, 0, 0),
709 .cmd_rcgr = 0x3360,
723 .cmd_rcgr = 0x3390,
737 .cmd_rcgr = 0x33c0,
751 .cmd_rcgr = 0x33f0,
765 F(100000000, P_GPLL0, 6, 0, 0),
766 F(200000000, P_MMPLL0, 4, 0, 0),
771 .cmd_rcgr = 0x3000,
784 .cmd_rcgr = 0x3030,
797 .cmd_rcgr = 0x3060,
810 F(133330000, P_GPLL0, 4.5, 0, 0),
811 F(266670000, P_MMPLL0, 3, 0, 0),
812 F(320000000, P_MMPLL0, 2.5, 0, 0),
813 F(372000000, P_MMPLL4, 2.5, 0, 0),
814 F(465000000, P_MMPLL4, 2, 0, 0),
815 F(600000000, P_GPLL0, 1, 0, 0),
820 .cmd_rcgr = 0x3640,
833 .cmd_rcgr = 0x2120,
846 .cmd_rcgr = 0x2140,
859 F(19200000, P_XO, 1, 0, 0),
864 .cmd_rcgr = 0x20e0,
877 F(135000000, P_EDPLINK, 2, 0, 0),
878 F(270000000, P_EDPLINK, 11, 0, 0),
883 .cmd_rcgr = 0x20c0,
902 .cmd_rcgr = 0x20a0,
916 F(19200000, P_XO, 1, 0, 0),
921 .cmd_rcgr = 0x2160,
934 .cmd_rcgr = 0x2180,
952 .cmd_rcgr = 0x2060,
966 F(19200000, P_XO, 1, 0, 0),
971 .cmd_rcgr = 0x2100,
984 F(19200000, P_XO, 1, 0, 0),
989 .cmd_rcgr = 0x2080,
1002 F(50000000, P_GPLL0, 12, 0, 0),
1007 .cmd_rcgr = 0x4060,
1020 F(19200000, P_XO, 1, 0, 0),
1025 .cmd_rcgr = 0x4090,
1038 F(50000000, P_GPLL0, 12, 0, 0),
1039 F(100000000, P_GPLL0, 6, 0, 0),
1040 F(133330000, P_GPLL0, 4.5, 0, 0),
1041 F(200000000, P_MMPLL0, 4, 0, 0),
1042 F(266670000, P_MMPLL0, 3, 0, 0),
1043 F(465000000, P_MMPLL3, 2, 0, 0),
1048 .cmd_rcgr = 0x1320,
1061 F(50000000, P_GPLL0, 12, 0, 0),
1062 F(100000000, P_GPLL0, 6, 0, 0),
1063 F(200000000, P_MMPLL0, 4, 0, 0),
1064 F(320000000, P_MMPLL0, 2.5, 0, 0),
1065 F(400000000, P_MMPLL0, 2, 0, 0),
1070 .cmd_rcgr = 0x1300,
1083 F(40000000, P_GPLL0, 15, 0, 0),
1084 F(80000000, P_MMPLL0, 10, 0, 0),
1089 .cmd_rcgr = 0x1340,
1102 .halt_reg = 0x5104,
1104 .enable_reg = 0x5104,
1105 .enable_mask = BIT(0),
1117 .halt_reg = 0x5100,
1119 .enable_reg = 0x5100,
1120 .enable_mask = BIT(0),
1134 .halt_reg = 0x2414,
1136 .enable_reg = 0x2414,
1137 .enable_mask = BIT(0),
1151 .halt_reg = 0x2418,
1153 .enable_reg = 0x2418,
1154 .enable_mask = BIT(0),
1168 .halt_reg = 0x2410,
1170 .enable_reg = 0x2410,
1171 .enable_mask = BIT(0),
1185 .halt_reg = 0x241c,
1187 .enable_reg = 0x241c,
1188 .enable_mask = BIT(0),
1202 .halt_reg = 0x2420,
1204 .enable_reg = 0x2420,
1205 .enable_mask = BIT(0),
1219 .halt_reg = 0x2404,
1221 .enable_reg = 0x2404,
1222 .enable_mask = BIT(0),
1236 .halt_reg = 0x348c,
1238 .enable_reg = 0x348c,
1239 .enable_mask = BIT(0),
1253 .halt_reg = 0x3348,
1255 .enable_reg = 0x3348,
1256 .enable_mask = BIT(0),
1269 .halt_reg = 0x3344,
1271 .enable_reg = 0x3344,
1272 .enable_mask = BIT(0),
1286 .halt_reg = 0x30bc,
1288 .enable_reg = 0x30bc,
1289 .enable_mask = BIT(0),
1302 .halt_reg = 0x30b4,
1304 .enable_reg = 0x30b4,
1305 .enable_mask = BIT(0),
1319 .halt_reg = 0x30c4,
1321 .enable_reg = 0x30c4,
1322 .enable_mask = BIT(0),
1336 .halt_reg = 0x30e4,
1338 .enable_reg = 0x30e4,
1339 .enable_mask = BIT(0),
1353 .halt_reg = 0x30d4,
1355 .enable_reg = 0x30d4,
1356 .enable_mask = BIT(0),
1370 .halt_reg = 0x3128,
1372 .enable_reg = 0x3128,
1373 .enable_mask = BIT(0),
1387 .halt_reg = 0x3124,
1389 .enable_reg = 0x3124,
1390 .enable_mask = BIT(0),
1404 .halt_reg = 0x3134,
1406 .enable_reg = 0x3134,
1407 .enable_mask = BIT(0),
1421 .halt_reg = 0x3154,
1423 .enable_reg = 0x3154,
1424 .enable_mask = BIT(0),
1438 .halt_reg = 0x3144,
1440 .enable_reg = 0x3144,
1441 .enable_mask = BIT(0),
1455 .halt_reg = 0x3188,
1457 .enable_reg = 0x3188,
1458 .enable_mask = BIT(0),
1471 .halt_reg = 0x3184,
1473 .enable_reg = 0x3184,
1474 .enable_mask = BIT(0),
1488 .halt_reg = 0x3194,
1490 .enable_reg = 0x3194,
1491 .enable_mask = BIT(0),
1505 .halt_reg = 0x31b4,
1507 .enable_reg = 0x31b4,
1508 .enable_mask = BIT(0),
1522 .halt_reg = 0x31a4,
1524 .enable_reg = 0x31a4,
1525 .enable_mask = BIT(0),
1539 .halt_reg = 0x31e8,
1541 .enable_reg = 0x31e8,
1542 .enable_mask = BIT(0),
1555 .halt_reg = 0x31e4,
1557 .enable_reg = 0x31e4,
1558 .enable_mask = BIT(0),
1572 .halt_reg = 0x31f4,
1574 .enable_reg = 0x31f4,
1575 .enable_mask = BIT(0),
1589 .halt_reg = 0x3214,
1591 .enable_reg = 0x3214,
1592 .enable_mask = BIT(0),
1606 .halt_reg = 0x3204,
1608 .enable_reg = 0x3204,
1609 .enable_mask = BIT(0),
1623 .halt_reg = 0x3704,
1625 .enable_reg = 0x3704,
1626 .enable_mask = BIT(0),
1640 .halt_reg = 0x3714,
1642 .enable_reg = 0x3714,
1643 .enable_mask = BIT(0),
1657 .halt_reg = 0x3444,
1659 .enable_reg = 0x3444,
1660 .enable_mask = BIT(0),
1674 .halt_reg = 0x3474,
1676 .enable_reg = 0x3474,
1677 .enable_mask = BIT(0),
1691 .halt_reg = 0x3224,
1693 .enable_reg = 0x3224,
1694 .enable_mask = BIT(0),
1708 .halt_reg = 0x35a8,
1710 .enable_reg = 0x35a8,
1711 .enable_mask = BIT(0),
1725 .halt_reg = 0x35ac,
1727 .enable_reg = 0x35ac,
1728 .enable_mask = BIT(0),
1742 .halt_reg = 0x35b0,
1744 .enable_reg = 0x35b0,
1745 .enable_mask = BIT(0),
1759 .halt_reg = 0x35b4,
1761 .enable_reg = 0x35b4,
1762 .enable_mask = BIT(0),
1775 .halt_reg = 0x35b8,
1777 .enable_reg = 0x35b8,
1778 .enable_mask = BIT(0),
1791 .halt_reg = 0x3384,
1793 .enable_reg = 0x3384,
1794 .enable_mask = BIT(0),
1808 .halt_reg = 0x33b4,
1810 .enable_reg = 0x33b4,
1811 .enable_mask = BIT(0),
1825 .halt_reg = 0x33e4,
1827 .enable_reg = 0x33e4,
1828 .enable_mask = BIT(0),
1842 .halt_reg = 0x3414,
1844 .enable_reg = 0x3414,
1845 .enable_mask = BIT(0),
1859 .halt_reg = 0x3494,
1861 .enable_reg = 0x3494,
1862 .enable_mask = BIT(0),
1875 .halt_reg = 0x3024,
1877 .enable_reg = 0x3024,
1878 .enable_mask = BIT(0),
1892 .halt_reg = 0x3054,
1894 .enable_reg = 0x3054,
1895 .enable_mask = BIT(0),
1909 .halt_reg = 0x3084,
1911 .enable_reg = 0x3084,
1912 .enable_mask = BIT(0),
1926 .halt_reg = 0x3484,
1928 .enable_reg = 0x3484,
1929 .enable_mask = BIT(0),
1943 .halt_reg = 0x36b4,
1945 .enable_reg = 0x36b4,
1946 .enable_mask = BIT(0),
1960 .halt_reg = 0x36b0,
1962 .enable_reg = 0x36b0,
1963 .enable_mask = BIT(0),
1977 .halt_reg = 0x36a8,
1979 .enable_reg = 0x36a8,
1980 .enable_mask = BIT(0),
1994 .halt_reg = 0x36ac,
1996 .enable_reg = 0x36ac,
1997 .enable_mask = BIT(0),
2011 .halt_reg = 0x36b8,
2013 .enable_reg = 0x36b8,
2014 .enable_mask = BIT(0),
2028 .halt_reg = 0x36bc,
2030 .enable_reg = 0x36bc,
2031 .enable_mask = BIT(0),
2045 .halt_reg = 0x2308,
2047 .enable_reg = 0x2308,
2048 .enable_mask = BIT(0),
2062 .halt_reg = 0x2310,
2064 .enable_reg = 0x2310,
2065 .enable_mask = BIT(0),
2079 .halt_reg = 0x233c,
2081 .enable_reg = 0x233c,
2082 .enable_mask = BIT(0),
2096 .halt_reg = 0x2340,
2098 .enable_reg = 0x2340,
2099 .enable_mask = BIT(0),
2113 .halt_reg = 0x2334,
2115 .enable_reg = 0x2334,
2116 .enable_mask = BIT(0),
2130 .halt_reg = 0x2330,
2132 .enable_reg = 0x2330,
2133 .enable_mask = BIT(0),
2147 .halt_reg = 0x232c,
2149 .enable_reg = 0x232c,
2150 .enable_mask = BIT(0),
2164 .halt_reg = 0x2344,
2166 .enable_reg = 0x2344,
2167 .enable_mask = BIT(0),
2181 .halt_reg = 0x2348,
2183 .enable_reg = 0x2348,
2184 .enable_mask = BIT(0),
2198 .halt_reg = 0x2324,
2200 .enable_reg = 0x2324,
2201 .enable_mask = BIT(0),
2215 .halt_reg = 0x230c,
2217 .enable_reg = 0x230c,
2218 .enable_mask = BIT(0),
2232 .halt_reg = 0x2338,
2234 .enable_reg = 0x2338,
2235 .enable_mask = BIT(0),
2249 .halt_reg = 0x231c,
2251 .enable_reg = 0x231c,
2252 .enable_mask = BIT(0),
2266 .halt_reg = 0x2320,
2268 .enable_reg = 0x2320,
2269 .enable_mask = BIT(0),
2283 .halt_reg = 0x2314,
2285 .enable_reg = 0x2314,
2286 .enable_mask = BIT(0),
2300 .halt_reg = 0x2318,
2302 .enable_reg = 0x2318,
2303 .enable_mask = BIT(0),
2317 .halt_reg = 0x2328,
2319 .enable_reg = 0x2328,
2320 .enable_mask = BIT(0),
2334 .halt_reg = 0x4088,
2336 .enable_reg = 0x4088,
2337 .enable_mask = BIT(0),
2351 .halt_reg = 0x4084,
2353 .enable_reg = 0x4084,
2354 .enable_mask = BIT(0),
2368 .halt_reg = 0x0230,
2370 .enable_reg = 0x0230,
2371 .enable_mask = BIT(0),
2385 .halt_reg = 0x0210,
2387 .enable_reg = 0x0210,
2388 .enable_mask = BIT(0),
2402 .halt_reg = 0x023c,
2404 .enable_reg = 0x023c,
2405 .enable_mask = BIT(0),
2419 .halt_reg = 0x022c,
2421 .enable_reg = 0x022c,
2422 .enable_mask = BIT(0),
2436 .halt_reg = 0x0204,
2438 .enable_reg = 0x0204,
2439 .enable_mask = BIT(0),
2453 .halt_reg = 0x0208,
2455 .enable_reg = 0x0208,
2456 .enable_mask = BIT(0),
2470 .halt_reg = 0x0224,
2472 .enable_reg = 0x0224,
2473 .enable_mask = BIT(0),
2487 .halt_reg = 0x020c,
2489 .enable_reg = 0x020c,
2490 .enable_mask = BIT(0),
2504 .halt_reg = 0x0234,
2506 .enable_reg = 0x0234,
2507 .enable_mask = BIT(0),
2521 .halt_reg = 0x0228,
2523 .enable_reg = 0x0228,
2524 .enable_mask = BIT(0),
2538 .halt_reg = 0x0214,
2540 .enable_reg = 0x0214,
2541 .enable_mask = BIT(0),
2555 .halt_reg = 0x0218,
2557 .enable_reg = 0x0218,
2558 .enable_mask = BIT(0),
2572 .halt_reg = 0x021c,
2574 .enable_reg = 0x021c,
2575 .enable_mask = BIT(0),
2589 .halt_reg = 0x0304,
2591 .enable_reg = 0x0304,
2592 .enable_mask = BIT(0),
2606 .halt_reg = 0x0308,
2608 .enable_reg = 0x0308,
2609 .enable_mask = BIT(0),
2624 .halt_reg = 0x502c,
2626 .enable_reg = 0x502c,
2627 .enable_mask = BIT(0),
2641 .halt_reg = 0x5024,
2643 .enable_reg = 0x5024,
2644 .enable_mask = BIT(0),
2658 .halt_reg = 0x5028,
2660 .enable_reg = 0x5028,
2661 .enable_mask = BIT(0),
2675 .halt_reg = 0x506c,
2677 .enable_reg = 0x506c,
2678 .enable_mask = BIT(0),
2692 .halt_reg = 0x5064,
2694 .enable_reg = 0x5064,
2695 .enable_mask = BIT(0),
2709 .halt_reg = 0x405c,
2711 .enable_reg = 0x405c,
2712 .enable_mask = BIT(0),
2726 .halt_reg = 0x4058,
2728 .enable_reg = 0x4058,
2729 .enable_mask = BIT(0),
2743 .halt_reg = 0x402c,
2745 .enable_reg = 0x402c,
2746 .enable_mask = BIT(0),
2760 .halt_reg = 0x4028,
2762 .enable_reg = 0x4028,
2763 .enable_mask = BIT(0),
2777 .halt_reg = 0x40b0,
2779 .enable_reg = 0x40b0,
2780 .enable_mask = BIT(0),
2794 .halt_reg = 0x403c,
2796 .enable_reg = 0x403c,
2797 .enable_mask = BIT(0),
2811 .halt_reg = 0x1030,
2813 .enable_reg = 0x1030,
2814 .enable_mask = BIT(0),
2828 .halt_reg = 0x1034,
2830 .enable_reg = 0x1034,
2831 .enable_mask = BIT(0),
2845 .halt_reg = 0x1048,
2847 .enable_reg = 0x1048,
2848 .enable_mask = BIT(0),
2862 .halt_reg = 0x104c,
2864 .enable_reg = 0x104c,
2865 .enable_mask = BIT(0),
2879 .halt_reg = 0x1038,
2881 .enable_reg = 0x1038,
2882 .enable_mask = BIT(0),
2896 .halt_reg = 0x1028,
2898 .enable_reg = 0x1028,
2899 .enable_mask = BIT(0),
2913 .halt_reg = 0x1430,
2915 .enable_reg = 0x1430,
2916 .enable_mask = BIT(0),
2930 .halt_reg = 0x143c,
2932 .enable_reg = 0x143c,
2933 .enable_mask = BIT(0),
2947 .halt_reg = 0x1440,
2949 .enable_reg = 0x1440,
2950 .enable_mask = BIT(0),
2964 .halt_reg = 0x1434,
2966 .enable_reg = 0x1434,
2967 .enable_mask = BIT(0),
2979 .halt_reg = 0x142c,
2981 .enable_reg = 0x142c,
2982 .enable_mask = BIT(0),
2996 .halt_reg = 0x1438,
2998 .enable_reg = 0x1438,
2999 .enable_mask = BIT(0),
3013 .halt_reg = 0x1428,
3015 .enable_reg = 0x1428,
3016 .enable_mask = BIT(0),
3033 .vco_val = 0x0,
3034 .vco_mask = 0x3 << 20,
3035 .pre_div_val = 0x0,
3036 .pre_div_mask = 0x7 << 12,
3037 .post_div_val = 0x0,
3038 .post_div_mask = 0x3 << 8,
3040 .main_output_mask = BIT(0),
3047 .vco_val = 0x0,
3048 .vco_mask = 0x3 << 20,
3049 .pre_div_val = 0x0,
3050 .pre_div_mask = 0x7 << 12,
3051 .post_div_val = 0x0,
3052 .post_div_mask = 0x3 << 8,
3054 .main_output_mask = BIT(0),
3059 .gdscr = 0x1024,
3067 .gdscr = 0x1040,
3075 .gdscr = 0x1044,
3083 .gdscr = 0x2304,
3084 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
3093 .gdscr = 0x35a4,
3101 .gdscr = 0x36a4,
3102 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
3111 .gdscr = 0x4024,
3112 .cxcs = (unsigned int []){ 0x4028 },
3121 .gdscr = 0x4034,
3297 [MMSS_SPDM_RESET] = { 0x0200 },
3298 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3299 [VENUS0_RESET] = { 0x1020 },
3300 [VPU_RESET] = { 0x1400 },
3301 [MDSS_RESET] = { 0x2300 },
3302 [AVSYNC_RESET] = { 0x2400 },
3303 [CAMSS_PHY0_RESET] = { 0x3020 },
3304 [CAMSS_PHY1_RESET] = { 0x3050 },
3305 [CAMSS_PHY2_RESET] = { 0x3080 },
3306 [CAMSS_CSI0_RESET] = { 0x30b0 },
3307 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3308 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3309 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3310 [CAMSS_CSI1_RESET] = { 0x3120 },
3311 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3312 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3313 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3314 [CAMSS_CSI2_RESET] = { 0x3180 },
3315 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3316 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3317 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3318 [CAMSS_CSI3_RESET] = { 0x31e0 },
3319 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3320 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3321 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3322 [CAMSS_ISPIF_RESET] = { 0x3220 },
3323 [CAMSS_CCI_RESET] = { 0x3340 },
3324 [CAMSS_MCLK0_RESET] = { 0x3380 },
3325 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3326 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3327 [CAMSS_MCLK3_RESET] = { 0x3410 },
3328 [CAMSS_GP0_RESET] = { 0x3440 },
3329 [CAMSS_GP1_RESET] = { 0x3470 },
3330 [CAMSS_TOP_RESET] = { 0x3480 },
3331 [CAMSS_AHB_RESET] = { 0x3488 },
3332 [CAMSS_MICRO_RESET] = { 0x3490 },
3333 [CAMSS_JPEG_RESET] = { 0x35a0 },
3334 [CAMSS_VFE_RESET] = { 0x36a0 },
3335 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3336 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3337 [OXILI_RESET] = { 0x4020 },
3338 [OXILICX_RESET] = { 0x4030 },
3339 [OCMEMCX_RESET] = { 0x4050 },
3340 [MMSS_RBCRP_RESET] = { 0x4080 },
3341 [MMSSNOCAHB_RESET] = { 0x5020 },
3342 [MMSSNOCAXI_RESET] = { 0x5060 },
3360 .max_register = 0x5104,
3393 return 0; in mmcc_apq8084_probe()